Overall looks very good but a few pointers which will make things easier to read especially when your circuits get more complicated.
You don’t need to join all the GND and +5V symbols together. For example EEPROM_Socket1, pin 4 - you can just place a GND symbol right at the connector instead of running a wire to common GND.
Same with all your decoupling caps. You could even move them completely out of the way in order to make the schematic easier to read.
Knitpicking here but useful to get this right from the start.
Positive voltage symbols generally point upwards and negative down so try to stick to this space permitting.
If i had to glance quickly at that I would think it’s -5V
On the PCB, not sure what current you are pushing through the tracks but you can make the GND/5V traces slightly thicker than the signal traces.
Look at setting up power net classes before you start layout out the tracks. (I only found out about this after 6 months after using KiCad
PCB Editor/File/Board Setup/Net Classes.
Create a new net class for Power with thicker tracks and then in assignments assign GND and +5V to that class. Then when you layout the tracks the power traces will be thicker than the signal tracks.
You should know what your manufacturer offers. I suppose that if such perforated line is only for you than no one cares, but if you want them to make scoring (not sure - I used dictionary - to make PCB thinner along that line) than you have to agree it with them.
When I ordered a set of 20+ small PCBs different sizes I placed them in 2mm distance (typical milling cutter used by my PCB manufacturer) and made it as a single PCB with 2mm gap with few small bridges over it and with so called mouse-bites. Here I found an example of it:
Other subjects:
most PCBs gain if you use GND zone,
VCC tracks width should be thought out.
For VCC connections I use many track width at the same PCB. For long connections I like to use 2mm track. For shorter and in crowded area it is not necessary so I use 1.3 or 1 or 0.7mm. To connect to small SMD pad I use even thinner (0.5mm) last track segments. For pull-up resistors (1mA current) I use 0.25mm VCC tracks to be able to go under 0603 resistors (imagine a 8 input set when each line have to be pulled up and go forward with the other resistor and you want to do it all using only top layer (bottom of my PCBs are continuous GND zone).
Does that also mean leaving them unconnected to the pinsockets in the schematic?
Coincidentally I was already doing that After my post and upload I was staring at it for a while and remembered watching the tutorial from John’s basement where he spoke up about the thickness. I’ve increased the main voltage paths, where pathing allows it. I didn’t know how to set up the netclass so I hit Q for every path I drew
Before I try and get this produced I will re-draw it from scratch (except the adjusted base footprint) with all the thing’s I’ve learned here!
Maybe I overdid it a little on the top track. Also I connected these with 90 degree angles. Somehow I feel this is “wrong” because I;ve never seen it on PCB’s as far as I can remember, but I don’t know why it’s “wrong”… just convention?
It is my rule for VCC with currents up to say 200mA (for 300mA I used wider track). Have in mind that if you are after regulator any voltage drop is left not corrected, but if you are before regulator any voltage drop will be corrected by regulator. 12cm is not very long.
You have already got my unswer:
The best is if GND zone can be continuous over all PCB (no tracks making its shape with islands or peninsulas). Here is my example of such design:
Before sending off the files to the PCB house, print a 1:1 and physically hold it over the Giga. Look for areas that don’t match or might interfere etc.
Make a feature to allow easy connection of a test instrument to ground. An extra hole or ground plane with no solder mask etc.
Great advice. Especially with connectors , relays, transformers etc Things that can be easily reversed in the process of transferring to a schematic. Most often I’ve found mistakes where the documentation isn’t clear if you are looking a the top or bottom view.
Back again with the latest. As I said I’ve started from scratch and hopefully did a better job this time. I could apply some of the things I learned from the start and hopefully that makes everything more tidy. The new version of KiCad also had a new symbol for the giga hat schematic wich simplified everything a little.
I managed to save my custom footprints, although fiddling with it prompts a popup about missing/removed .pretty files. Those footprints are no longer used in the project so I hoped that popup would vanish as well but no such luck.
The ERC gives some warnings about intersecting lines and thermal relief but I don’t think they are actual problems.
I’ve added in the front and back GND plane, added via’s to connect them and moved some connectors to sit closer to the pins they connect to. Also added some new things and tried to optimize what I could. Got the mousebites in and drew a line on there on plane user4 that is supposed to be a V-grove for easy seperation. I’ll email jlpcb (seems the easyest option for now, and I’m in the EU) about how I would make it clear it’s supposed to be a V-grove. At least in the 3D render it looks exactly like I wanted it (after struggling a lot with the courtyard lines).
One final question about the ground of the barrel jack connector: should it go to the common ground or as a seperate line to the designated ground next to the Vin?
In my opinion it depends if Power section in the biggest rectangle at schematic is linear (than ‘don’t care’) or DCDC (ten keep the current pulses out of common ground).
At schematic:
If I see for A10 and A11 R1 ind R2 going up I understand them as pull-ups what is not true in your case.
5V1, 5V3, 5V4 all are connected together by +5V power symbols. So why not connect them all together and delete the wire going form 5V1 to +5V.
Placing additional +5V symbol near them you can also avoid +5V wire going toward J11.
The same with GND wire from GND1…GND6 to R2 (then R1, and R2 could have GND not over them but under them).
As you have signal lines at top and bottom then if you expect fast signals there I would consider adding two internal layers and making them continuous GND.
I have never ordered anything at JLC - I don’t know what is the price difference between 2 and 4 layers.
I’m not sure what fast signals are. There will be 4 I2C sensors and 2 DHT22 sensors on the digital pins. I suppose they don’t need extra layers of GND?
@paulvdh & @JohnRob absolutetly printing it on paper first, thanks!
edit: also spotted and corrected a mistake at the RJ25 connectors, connecting both SDA and SCL to +5V after movinging them around.
I just don’t remember what was said 22 days ago and seen EEPROM text at PCB so assumed that may be it is EEPROM with fast interface (say 10MHz).
Now I found that it is also I2C.
So probably you don’t have very fast signals at your PCB.
It was intentionally conditional sentence - it is you who knows how fast your signals are.
Unfortunately fast is most about rise/fall time and not frequency.
In 90s we designed some education PCB with serial EEPROM connected to it by 10 cm flat cable. Everything worked. 10 years later we assembled a next serie of these devices and we had a problem with EEPROM (exactly the same type as previously). It was simply manufactured with smaller (cheaper), faster process and its output had shorter rise/fall time. When EEPROM switched its output one of slopes was fast enough to make very short pulse at clock line (in that 10cm cable) and EEPROM was enough fast to react for such very short pulse receiving extra pulse at clock.
Generally every digital signal line like to have return path just under it and continuous GND gives it.
But with I2C you will probably have no problems.
After my post and upload I was staring at it for a while and remembered watching the tutorial from John’s basement where he spoke up about the thickness. I’ve increased the main voltage paths, where pathing allows it. I didn’t know how to set up the netclass so I hit Q for every path I drew 
