@1.21Gigawatts Thanks, I just updated the OP with images of the schematics.
If I understand correctly, I should put a decoupling cap right next to the VCC pin on the atmega, and the caps legs should be between the VCC and GND copper pours. Should I have more decoupling caps anywhere else, and how do I figure out what rating the cap should be?
I will dig around for cleaning up vias and GND planes. Once I figure that out, and find out about decoupling caps, I will post new gerblook links as a reply.
1.- General rule: Do your traces as thick as possible. In your design ¿Is there a reason to make them that thin? No matter that your PCB manufacturer is able to deal with 3 mil traces, make them thicker than that.
2.- Are you going to use wave soldering or hand-soldering instead? The pad’s sizes depend on that. In your design, it seems to be wave-soldering. For hand-soldering the pad’s sizes should be larger (diameter >100 mil, 125mil works well).
3.- There are lot of space unused. Why don’t you fill it with polygons? Maybe for a ground plane.
4.- When possible use vertical traces on the bottom cupper side, whilst horizontal ones on the upper cupper side.
5.- Clearance seems to be ok, but as with traces, the more space among tracks, the better for your design and for your manufacturer’s tests.
The fastest way is to edit directly the footprint. There you can modify the pad’s sizes according to your needs (as said before, for me pad’s size is ok between 125 and 150 mils).
You can do that as this on your design:
1.- On the Footprint editor create a new component based on an existing one, for example, a LED, and give it a distinctive name.
2.- Back on your PCB, right click on one LED. Then Properties and Change footprint. Choose “Change footprints ‘LED’” (or whatever the LED footprint name has been given). Finally write the name you used on step 1 in the text-box “New footprint (FPID”. And voila! all LEDs footprints has been changed.
3.- Repeat the procedure for all components. Save them all on a common library for being used in the future.
@Joan_Sparky so from what I gather, I should have a 10uF ceramic capacitornext to my power supply in this case, the power boost 1000c, and a .1uf tantalum capacitor next each vcc pin on any of my ICs? Does that sound right?
Everything suggests using SMT caps, but would there be any issue with using THT caps?
1.- In your microcontroller do no put 1 bypass cap, but 2 instead: one 100nF and one 10nF in parallel.
2.- If you have decided to place a GND plane, make it in both cupper sides; and if you notice not connected isles, connect them with GND traces and repour the polygons.
3.- For GND plane you might use 20 mil clearance.
4.- Power traces should be as thick as possible, even twice from the calculator values.
5.- 90 degrees traces could lead to reflections and manufacturing problems … Think for a moment in a water pipe with 90 degrees corners: the water pressure will decrease with this kind of corners; same with electrons. That’s way 45 degrees corners are prefered.
5.- Traces from the crystal to the microcontroller should be as thick as possible. Also add a ground plane that surrounds the crystal, the caps and the crytal’s pins (check what your microcontroller’s manufacturer has to say about this in the user manual).
So after digging around a bit, I realized the powerboost and the Bluefruit LE UART Friend, since they are separate PCBs, do not need bypass caps, because they have them built in. As a matter of fact, the bluefruit has a 10uf, then the 3.3v converter, then another 10uf, and finally a 1uf cap, while the powerboost has a 2.2uf and then a 100uf on its power output.
I assume that means my power supply (the powerboost) does not need that separate large cap.
Here are the schematics I used to figure this out:
Over the years I was putting together a kind of checklist at: http://www.blunk-electronic.de/pdf/Design_Checklist_en.pdf
It is not only relevant for EAGLE-designs but for general issues as well. I look forward to read your feedback.
You generally use a Vcc plane when the current intensity in your circuit is expected to be very high. Besides that, a Vcc plane (aka power plane) is put in the internal layers (for 4 o more layers).
Also, you HAVE NO CONTROL on the capacitor that is created when ground a power planes are used together.
Ground plane helps with parasitics and EMI transmission/radiation.
No, I meant wave-soldering (or wave solder). He is using PTH in one of the boards (the one with LEDs).
I hadn’t seen the other boards, and in fact, for those with SMD components one MIGHT use paste reflow as you’ve pointed it out, or hand-soldering as well.
Signal tracks still look awfully thin for a THT board - what’s their width (mm or mil)?
VCC/GND are well taken care off.
PS: might be a little late to ask this, but how are you programming the AVR?
Atmel has defined an interface for that (ISP) which you might want to implement/use… if you get one of those AVRispMkII clones to do this etc. you can even debug the MCU in-situ.
@Joan_Sparky thinnest trace is 10mil. With a 10deg allowed thermal rise this can handle around 3/4 of an amp, well above the predicted draw on my lines (with the exception of power rails, I cannot think of anything drawing over 40 milliamps.
As for in circuit programming, I am not using ISP because of pin requirements of my project. I have instead opted to use the RX/TX pins. Since the chip already has the Arduino bootloader, I can reprogram the chip over that. In addition, I do not know how to use the in-situ debugging, so there is no point for me to set that up.
