First project, can someone look it over?


#1

I just finished designing my first project for fabrication, and I was wondering if anyone would mind looking over my project to see any possible errors.

Major issues I am worried about:

  1. Traces too small
  2. Traces connecting to the wrong thing, risking shorts
  3. stuff too close together
  4. Anything that catches you eye that could result in a failure to have the board work.

There are two boards in this project. One is a control board that uses an ATMega328 to read data from a bluetooth reciever and then trigger pulsing signals on the MCP23017 port expanders.
The other board recieves signals from the port expander and transfers them to LEDs.

To make things simpler, I am linking to GerbLook.

Note that the one labeld Control Board no expansion header is outdated, and does not need to be checked.

Main Control Board: http://gerblook.org/pcb/TEZvxUUxGeCqAtk7xtSBZc

LED Board: http://gerblook.org/pcb/qSMwnkTW7ecKrxJngZ98yV#front

Photos:


Layout check for errors
#2

BTW: Use $KIPRJMOD variable instead full path in your local fp-lib-table files.


#3

Hi Keruseykaryu,

I know this is a KiCad forum and all but I think you would get a lot more help if you just post screen grab picture of the schematics and PCB layouts. Its quite an effort to download and setup your project files for a full review.

Regarding your major worries

  1. Trace width is dependent on factors like your PCB fabricators capabilities, the current carrying capacity of said traces and any required impedance characteristics you may need.
  2. This is going to need a full system review and probably out of the scope of the most generous contributor on this forum. Have you performed ERC in the schematic and DRC in pabnew?
  3. See 2.
  4. Basically welcome to the world of electronics design. Anything is such an open ended question. Typically anything can and will go wrong.

#4

I can upload photos. What would be the best method? All photos on a page? Copper Pours On/Off? Two photos, one with each layer on top?

I have run ERC/DRC.


#5

A popular method in some IRC fora when seeking design feedback is to generate gerbers for a design and post them to a website such as:

http://gerblook.org/

Then post the link,

Gerblook’s backend is gerbv, and does a pretty good job of rendering layers.

IIRC, there may be an issue with slot rendering as it is an older version of gerbv, but otherwise it is a handy means of making a design available for review by many.

You generate your gerbers, zip them, and upload.

It is worth having gerbv on your own system to review gerbers as well, before sending them off.

http://gerbv.geda-project.org/

gerbv will sometimes show things that aren’t obvious in the PCB layout tool.

Incidentally, an acquaintance who used to work for a large electronics company in PCB fabrication talks about his “rule of 4”. You’ll spot 4 errors in your layout once the board has been made :slight_smile:

His other pet gripe is the use of traces that are un-necessarily thin, wasting etchant and resources during manufacture.

Cheers,

Erich.


#6

I added a screenshot of the control-board layout to the OP.
To me it looks alright in regards to spacing and overall layout…


#7

I have added Gerblock links for the two boards to the OP.


#8

The only things I would be tempted to do with that layout, if I were sending it off to be made, would be

  1. to fatten up the signal traces where possible. Fatter traces are less prone to lifting off with excessive soldering iron application, or rework of the board subsequently. It also wastes less etchant, from the fab’s perspective.

  2. put a design revision number on the layout too. If you do another version of the board, it’s less confusing for everyone when it comes to sending off the gerbers.

  3. there’s plenty of room. You could put part numbers within or adjacent to the particular footprints on the silk layer.

Cheers,

Erich.


#9

@erichVK5 Thank you so much, any advice on how fat the signal traces should be? They are currently around the fab houses minimum.

So you see no glaring electrical issues?


#10

I routinely use 40 mil traces as a default signal width in simple, low speed stuff, but some people used to the minimum thickness lines think it looks a bit like EDA brutalism. Obviously this makes routing between pins and more compact layouts harder. In your case, fattening up some of the parallel traces might require them to be spaced apart more too.

Others no doubt would have different opinions on default widths.

Wider traces might are also more suited to home etching, especially if drilling.

You might want to put the relevant licence on the board too, if it is an open hardware project.

Cheers,

Erich


#11

If I recall correctly, the board fab used by my employer likes to see (minimum) 8 mil traces with 8 mil spacing, although 6 mils is still considered a “standard” job. Since all of the boards I have done with KiCAD are manually assembled, I use 20 mil traces wherever possible and try for 30 mil spacing, although it’s not uncommon to settle for 20 mil spacing or sometimes even less. (Especially when passing traces between component pads.) Many of my footprints have over-sized pads to make room for a soldering iron tip.

Dale


#12

Just measured some circuit boards near me. 20mil seems fairly common. I will bump it up to that, and bump up the corresponding vias as well.


#13

[quote=“erichVK5, post:8, topic:6412”]
2) put a design revision number on the layout too. If you do another version of the board, it’s less confusing for everyone when it comes to sending off the gerbers. [/quote]
This is VERY sensitive to the “house rules” of your employer or client. Unless I’m told otherwise I put the bare board’s part number and rev level in copper on the back side, and the assembly’s part number on the front-side silkscreen - with a rectangle or oval of silkscreen ink where the assembly rev level can be noted with permanent marker.

Putting part numbers or values on a board can be helpful for manual assembly or subsequent repair activities but it’s also problematic, since this information may change during a product’s production lifetime. (E.g., when purchasing gets the BC860 transistors from a different source, a 1200 ohm emitter resistor may give better performance than the original 1500 ohm resistor.)

Dale


#14

Yes, many of us probably had a good laugh when we saw that assignment. Nothing is ever fool-proof, because we fools are VERY ingenious!

Dale


#15

What would be the risk of not making the traces that big?
A .1mil trace can easily handle 500 mA (according to http://www.circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/), which is well over my max draw in most cases.
I am going to manually assemble this, but going back and changing the trace width of every single trace (especially on the control board), is basically just completely redoing this project, and I am on a bit of a deadline.


#16

1mil trace can easily handle 500 mA

My first thought was “I don’t think so…” Statements like this will get you in trouble, because they are (nearly) always predicated on a set unstated assumptions. Length of trace? Copper thickness? Internal or external layer? Ambient temp? Allowed temp rise on the trace?

Using a 1" length trace in 1 oz copper on an outer layer with a 10C rise allowed at 25C ambient, that calculator you mentioned said it would need a 4.55 mil trace width. To get to a 1 mil trace you would need the temp rise to be more like 120C – not a good idea, IMO. Perhaps you meant 0.1mm trace width (~3.9 mil)? That would be at least in the ballpark of reasonable.


#17

My bad, I meant 10mil, not 1mil. That would be absurdsly small and I would be hard-pressed to find a fab house that can even handle that.

My question still stands: What would be the risk of making traces 10mil and seperation 10mil?


#18

Updated a bit. Now it has 10mil traces, and separation is never less than 10mils. Here is the GerbLook link: http://gerblook.org/pcb/zzZhdL3iLDrW7Qdvmz6Kg5

Also, when I said anything that causes an error, I mean anything that anyone catches with their eyes. I know more eyes means less of a chance of a mistake.


#19

It looks pretty good.

I am having trouble discerning if the copper pour on the underside is all ground plane or not, or if there are islands of isolated copper hanging off of long ground or signal/power runs. For low speed stuff it may not matter wrt EMC/RFI etc.

I gather people sometimes make a footprint containing a pin for use as a stitching via to join ground planes. In gEDA PCB/pcb-rnd you can drop a stitching via to join pours where-ever you like.

Not much else comes to mind.

Cheers,

Erich.


#20

I do not follow 100%.
The copper pour on GerbLook’s bottom copper layer is VCC, and on top copper it is GND.

I am not sure about what counts as low speed and high speed. That is another question I had. This project will have I2C and UART communication, the code controlling the MCP23017 I2C port expanders has them changing the state of the LEDs as rapidly as every milisecond (or slower if the ATMEGA328 is not able to handle that), the serial port between the bluetooth chip and the ATMEGA is at 9600 baud, while the FTDI pin connection is at 115200 baud (though I could slow this down to 9600). Could any of these be fast enough to cause possible adverse interference?

On a totally unrelated note, I have never seen a copper trace do a perfect 90 degree turn. Is there a reason for that, or is it just simple because 45 degree turns look better?