Thanks, i thought it would be ok to post this in the projects category, i can delete if such things are not allowed 
As a first attempt, I’ve seen worse.
Space parallel tracks as much as possible where there is no space constrains. And do yourself a favour, use a 4 layer with ground and power plane. There is a recent post that explain how an why.
Thankyou so much for the feedback, it is most appreciated.
Yup, top layer, ground plane, power plane then bottom signal layer
I don’t know your track width, but thinner tracks for signals are generally better. Thicker tracks just add capacitance, and that increases power consumption. a 0.2mm track can already handle 700mA (with a 10 degree temperature rise) The usual limit is what your PCB manufacturer can manufacture (and for what price) and it’s generally advised to make tracks a bit thicker as the minimum they post on their websites.
Track width is set at 0.25mm except where its power and ground which ive increased to 0.5mm
If you do the horizontal part in a different order, then you spread the capacitive coupling between the tracks, and this spreads crosstalk
Ah i see what you mean, thankyou, ill flip them over.
All those via’s make a big cutout in the GND layer, and that is not good. It’s much better to either spread the via’s more so GND can stay between them all, or make small groups of via’s.
This makes sense, that whole bottom area need a lot of tidying anyways so ill spread them out when i do.
I am also guessing this is a PCB with relatively slow logic. If you want to do fast logic, such as DDR3 or DDR4 then you also need to do things like controlled impedance and delay matching.
32mhz is the fastest signal on the board.
The question is more about rise time than digital frequency. The digital frequency is independent of the rise time. Well you need a minimum edge steepness for a given frequency but the steepness can be way higher than you would assume from the digital frequency.
And 32 mhz ? Are you sure? What is that unit even? 32 mHz ? (0.032 Hz) Or 32 MHz ? (32’000’000 Hz)
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Since this forum has an explicit category for projects done using KiCad, I would imagine this post is OK. But what do I know…
Also, +1 for “destructive criticism”.
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Traditionally KiCad screenshots have bribed the moderators for starters, and the attached project does the rest.
With a bunch of milli Hz you’re still pretty close to DC. But it is not the clock speed that counts, but the steepness of the signal flanks that deterimines the frequency content of the signals, and thus the quality of the necessary PCB layout. for this reason, a lot of modern logic, from uC’s to FPGA’s have configurable I/O win which the drive strength is adjustable.
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“Use this category to talk about projects, but try to mention how KiCad is playing a part in the design.”
That would be a maybe.
A post such as: “I want to design XXXX using Kicad, how should I start?” should receive the reply " Show us what you’ve done in Kicad" first. If nothing, close with a link to “Beginners Guide”.
A post with a Kicad schematic and/or PCB with a “what do you think of this?” should pass scrutiny.
I generally think that clear electronic discussions can be closed as there are probably better places for them. But PCB related discussions, even not strictly based on KiCad, in my opinion should have place at forum as learning to use KiCad is directly connected with learning to design PCB.
During last 2 days I was wondering if my discussion about DCDC converter design started with ‘Are you sure’ in this post:
fits into the forum topic.
The discussion of which way AC signals in DCDC flow is strictly related to how PCB should be designed - which connections are critical and which less critical. And even it is not related to KiCad I think it is helpful to users learning KiCad. I am still learning KiCad and that discussion gave me some new knowledge - I will look little differently at routing DCDC converters.
My 2 cents:
- At top left of picture. If you have +5V at inner layer than pin 22 connection to C1 is not needed.
- It looks that there are enough space to have tracks between pads of that IC on the left. not sure, but may be it can be helpful.
- Top left pin of the IC in the center looks being connected to +5V (I see connection line). If you have +5V layer then what for is that pin routed right and then down out of picture. It should be connected as that connection line shows and nothing more.
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Here is a good read about “Transfer Via’s”, which are vias between GND layers used when signals go though a via and therefore their return paths get referenced to another GND layer. Especially the simulations in the video from Robert Feranec are enlightening of what sort of stuff happens with the current path though GND layers in a PCB.
From that video It should also become clear why 2 GND layers are preferred abov a GND and a power layer.
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Thanks for this, that is really helpful to understand what is going on.
So…If its a 4 layer board with 2 ground planes, where would the power go? on the top signal plane, sorry if i misunderstood the recommendation.
Ok another 5 hours and ive reworked it for the 5th time and i think its looking a lot better… Really enjoying Kicad, its helping me learn a lot.
So based on the article you linked to i should be splitting up this row of vias into say 3 groups instead of a solid block of them right?
For years I used to design 2 layer boards with whole bottom destined to one continuous GND zone. So all signal and power lines were at top. From time to time I had to use some 0Rs.
Here is the example how it looks practically (all vias are GND):
Now when I started to design 4 layer boards I have In1 and In2 GND, signals at top and VCC at bottom (I have only VCC and GND vias). But my designs (as you can see in the above example) are simpler to be routed than yours. But even with your circuit there probably will be no problem to route signals and power having 2 layers for it.
I have a strong preference for a 4 layer board with 2 ground planes, over a 4 layer board with a power and a ground plane. The strongest reason is that both ground planes can be stitched together with via’s, so interruptions in one ground plane can be repaired by the other ground plane, so the loop area of the return current is minimized.
To answer the question, I would try to put the power traces at the top or bottom signal layers, and then put short power traces in one of the middle layers then it’s not possible to route it all on the signal layers.
Every time a trace is placed in the ground plane layer, it must be stiched with via’s, so he return current has as little loop area as possible.
Please refer to this pdf for more information about ground planes:
http://www.elmac.co.uk/Lord_of_the_board.pdf
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