or just buy them already done for less than a buck a board:
IIRC there is a known problem with these – if you crank the pot to one end you can exceed voltage on fb and blow the chip. Best replace the pot with a divider.
Yes that is a known issue
That issue can be relaxed if I use another series resistor with pot but result in caped minimum voltage
I am mainly making it for learning purpose
I happen to have a entire reel of MT3608L from a assembly line ( rejected reel but most are in spec)
Your PCB fabricator will thank you for leaving it in . . . less etching to be done.
That what the impression I got from my local fab
Yes it dose have ground plane is a 2 layer board design
Noise is certainly a concern which I have no way of testing and very
I can only lean on to the basic design and data sheet recommendation and advise from other
Also what do you mean by top side GND ( close to L1 & D1 )
I have a GND strip there and bottom PCB is entirely cover by GND
I would do one GND zone for top layer and not 3 separate zones. Probably with some restricted area around SW net to limit capacitance from that net to GND.
I think that when it will be filled a thin but short copper connection from IC pin 2 to input capacitors will be added. It will short the current loop in both DCDC phases. Even it can have higher resistance than going through your vias and through bootom GND to the vias to input capacitors it will have lover inductance so the higher harmonic of current will have the shorter way back.
I look at DCDC design that way that I imagine current loops in two phases and assume that they are blinking (only one lights at one moment). And my task is to make the distance of looking at that PCB when I not notice blinking as short as possible.
In my model both current loops are going through L so you can add some tracks to it with no influence on blinking.
Are you sure?
For me from ground it goes back to input capacitors GND pins and it has an unnecessarily long way because of via for input capacitors being placed not in the shortest way to them.
As I’m not power designer I’m trying to assume that you are right - may be you are thinking about some current flowing through MOS as it is not fully switched off yet but then it should rather be understand as a tail of current flowing when transistor is on then to be understand as the way of current (even the highest harmonics) flowing when transistor is switched off, I think.
I agree with it. The need for supply with variable output voltage is rather rare. Consider using not variable voltage divider. But if you really need it then better would be to have variable resistor in connected to GND part of divider (in serie with resistor limiting its minimum value). Loosing linearity of regulation you win safety.
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My only “opinion” on this is look at the loop associated with the ON period. The current loop will be:
J1 → L1.1 → L1.2 → U1.1 → U1.2 → J2
During the OFF period it will be:
J1 → L1.1 → L1.2 → D1.1 → D1.2 → J3 → J4 → J1
The OFF loop looks ok but I wonder if there is anyway to improve the ON loop. The only reason I am wondering is the OFF-loop current return will go via the … via’s under the feedback signals and it might pick up some noise. Its the OFF period so it should freq-limited and thus it will just wait until the next control cycle.
Apart from that, nice little switcher.
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Where exactly is the restricted area near U1 &L1
is it at bottom side of PCB ?
If I use via to giv output voltage to feedback resistor
Then I should be able to reduce GND on front layer to only 2
That upper one GND I believe have no effect of rest of PCB
For safeer variable voltage is it
VOUT > fixed resistor > IC > fixed resistor > POT > GND
I am really really sorry for all the trouble in all this this is my only 5 days of work on this PCB and 1 weeks of research on PCB
And very glad to have all this advice and feedback 
Thanks for kind words
I am not really sure
If I use via to giv feedback loop VOUT
The the GND from output caps and U1 GND will be connected to directly main GND ( VOUT AND IN GND)
But using via to use for feedback on 2 layer board is it desirable?
Don’t use a fill on the switch node. It is very noisy and will radiate everywhere. Use tracks only for connection.
It looks that you don’t fully understand how zones work. You need not to create zone islands at top yourself - they will be created for you by KiCad.
Just draw GND top layer zone around whole PCB (zone bigger then PCB) and see what will happen after zones will be filled (hotkey ‘b’). It is what I was thinking writing about one GND zone.
When adding zones I typically set Clearance to 0.25, Minimum width to 0.2, and Thermal relief gap and thermal spoke width both to 0.25.
When you will see how zones work you can think that zone fill is going to close to your SW net. Because of it you can add around your SW net an area with only “Keep out copper fill” set.
I’m not power designer and I have doubts if such protection should also be set at bottom or not. Typical PCB thickness is 1.5mm. It is 6 times bigger distance then 0.25 mm Cleranace at top.
Argument to restrict GND here at bottom - to make capacitance from SW node to GND smaller.
Argument to left solid GND at bottom - it works like shielding making emissions from SW net smaller.
And I don’t know who is the winner.
Yes. If POT lost contact during regulation you will get smaller voltage at output and not the highest IC can generate.
You need not to be sorry. If someone wants to answer your questions it is his (also mine) free will. Nobody forces anyone to do anything so it’s not your responsibility if someone wants to spend time on it.
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Yes I don’t think bottom PCB need any changes that won’t be worth at such a small node
And as for filling zones that is a little bit dark area that I need to know
A keep out zone from to sw node to U1 seems ?
I think I should add that POT to GND to it
MT3608 have tendency to burn when voltage gose up very quick I only need range of 5v to 15v at max
If you have different zones one at another they can be shorted if they both have the same priority level (order of creation).
In KiCad V5 when you added zones they got by default the same priority. Now (since V6 or V7, I’m not sure) they got different priorities but you may want to change their order.
I don’t understand your doubts.
I was not speaking about node but about net (= all nodes connected to that net + all tracks making this connection). At your fist picture there are net named ‘SW’. I don’t know where from you get that name as at schematic there is no ‘SW’ label that would be normally used to name that net.
Do you really need it being regulated? Isn’t it better to make several such PCBs and set each one a different voltage by using right resistors and not POT. If you need you can desolder such resistors and use others.
Yes circuit do have those nets I just hid the labels
Useing several board is a long term solution
I just was just want it variable 
no solid reason
Will make a small revision in few days let’s see how it turns out
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Yes! In a boost converter, the input current all passes through the inductor, so there is not so much activity at the inductor input. The switching happens at the inductor output, and that is where the “hot loop” is.
In a buck converter, the hot loop is at the input of the inductor.
Yes I have been doing this for > 40 years but I would greatly prefer to explain it adequately as opposed to asking you to take my word for it.
Solid ground plane as you show ought to be good. I was trying to say that the ground plane ought to at least cover the bottom side copper area underneath the “hot loop” that I described.
Funny…I google the topic “boost converter hot loop” and this came up near the top. Maybe because google knew it was me and found my name…
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Is that anything like a buckboard?
Makes no sense but funny as heck! 