I would do one GND zone for top layer and not 3 separate zones. Probably with some restricted area around SW net to limit capacitance from that net to GND.
I think that when it will be filled a thin but short copper connection from IC pin 2 to input capacitors will be added. It will short the current loop in both DCDC phases. Even it can have higher resistance than going through your vias and through bootom GND to the vias to input capacitors it will have lover inductance so the higher harmonic of current will have the shorter way back.
I look at DCDC design that way that I imagine current loops in two phases and assume that they are blinking (only one lights at one moment). And my task is to make the distance of looking at that PCB when I not notice blinking as short as possible.
In my model both current loops are going through L so you can add some tracks to it with no influence on blinking.
Are you sure?
For me from ground it goes back to input capacitors GND pins and it has an unnecessarily long way because of via for input capacitors being placed not in the shortest way to them.
As I’m not power designer I’m trying to assume that you are right - may be you are thinking about some current flowing through MOS as it is not fully switched off yet but then it should rather be understand as a tail of current flowing when transistor is on then to be understand as the way of current (even the highest harmonics) flowing when transistor is switched off, I think.
I agree with it. The need for supply with variable output voltage is rather rare. Consider using not variable voltage divider. But if you really need it then better would be to have variable resistor in connected to GND part of divider (in serie with resistor limiting its minimum value). Loosing linearity of regulation you win safety.