At least I thought I was finished until I ran the DRC…82 errors and 5 warnings. I am too tired now to check the errors, but it looks like a bunch of them are about the footprints I got from the Digi-Key library. Also several warnings about traces with no end connections. Aargh.
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I am not sure if my experience is representative, but I would be surprised as heck if I did not have a large number of DRC errors and warnings when checking a board. For me, a big piece of it is understanding what to ignore and what to take seriously. My last two boards work nicely, and the errors are ones which DRC would not have picked up anyway. I use pretty much all of my own footprints.
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Run the trace cleanup tool to get rid of some of the stray trace warnings.
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The trace cleanup tool is awesome. You’ll probably find that in those 82 errors it’s 8 errors, repeated 10 times. So as you go through them, regular re-run DRC and see what’s remaining.
Imported footprints (even from the native library) are indeed a common source of errors - even the best footprints don’t know your particular design rules, so it’s possible to have a good footprint that nonetheless fails your rules. Or the footprint might just suck - tending to footprint libraries is an art. By and large the error is a good thing - your rules should be set to match your manufacturing capabilities, so if the footprints are triggering it it’s better you know about it now!
I’m a fan of only ignoring errors and warnings as a last resort. As I said, you probably only have a dozen or so root causes, and for each one it’s worth deciding:
- this is fine, my design rules are too stringent
- this is fine, my footprint is just too conservative (eg. the courtyard is excessive)
- this is an issue
Then I’d do:
- adjust the design rule
- adjust the footprint
- adjust the design
respectively, until the error goes away. If you take this approach early on, you’ll find that the DRC starts to give you really useful results. If you ignore them early on, you might find that they build up to the point where you’re sifting through hundreds of errors looking for one that matters.
The times I have ignored them are when I was doing something funky, like hanging a part over the edge of the board. Even then there’s usual ways to mitigate the error. Besides, I’m sure most designers have a story about how they ignored some silly courtyard error, and then ate their hat when they discovered the courtyard took into consideration some assembly detail they’d overlooked!
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Thanks Heath. It’s nice for a newcomer to KiCad (me) to get a summary of DRC issues and how to handle them.
I followed your suggestions and successfully cleared all the errors and warnings without changing any of the design rules. It turned out to be easier than I anticipated. In fact, there were only two types of problems.
The first type was associated with the 48-pin LQFP, specifically that the courtyard was self-intersecting. As it turns out, the problem was that the lines for the courtyard were drawn twice, one set directly on top of another. When I removed the top set of lines, the problem was solved.
The second type was simply that the references for many of the parts were touching one or more pads of a part. I moved the references, and all the errors disappeared. Is it interesting to note that references that touched traces didn’t produce errors, only the ones that touched pads. So all in all, it was pretty easy to resolve all 82 errors and 5 warnings.
A screen-shot of the PCB is attached for those of you who are interested. Everything is made visible, so it looks jumbled, but it really is not bad.
I can certainly see that KiCad is more feature rich than DipTrace, but I don’t know that it will make my PCBs a lot better.
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That’s because traces will be covered by solder mask which can be printed on, but pads are exposed.
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Yes, that’s correct. I was mislead by the explanation of the error:
[silk_over_copper]: Silkscreen clipped by solder mask
It would be more accurate to say as follows:
[silk_over_copper]: Copper clipped by silk screen
“Silkscreen clipped by soldermask opening”, or “Silkscreen removed in soldermask opening”.
Copper is never clipped (removed), only silkscreen is where there is exposed copper and in the margin between exposed copper and the edge of the soldermask, if the soldermask opening is larger than the copper (can be the case).
I didn’t realize anything was removed; I took “clipped” to mean “touched.” Is the silkscreen actually removed? If so, it must be in production or when the Gerbers are generated because none of the silkscreen is removed in the on-screen images in KiCad 6.
Well just read that as silkscreen clipped by edge of solder mask.
Yeah, depending on your manufacturer it ends up looking a bit like this:
But the “depends on your manufacturer” is the key bit - KiCad can’t predict what will actually happen, and technically your manufacturer doesn’t have to remove it. In that case, much worse things can happen, like this sorry tale:
That’s why the warning is so important - KiCad is essentially saying the result is undefined, so beware!
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How about “silk screen overlaps mask opening”? Would that be understandable for everyone, exact and unambiguous?
When generating Gerbers you can choose to remove silk screen on mask openings.
Edit: silk_over_copper still conflicts with the explanation. It should add “potentially” or something like that…
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the lines for the courtyard were drawn twice, one set directly on top of another.
I find this happens for every computer-generated footprint from SnapEDA or UltraLibrarian (which are usually linked from Digikey).
Does anyone know why? Or is there an easy way to simply remove the duplication? Currently my workflow when verifying a footprint involves just deleting the duplicates manually but it’s tedious and occasionally forgotten.
That is interesting to know. It took me a while to find the problem; at least from now on, I will know what to look for. BTW, I think the footprint did come from one of the sources you mentioned, but I don’t remember which one.
It is unambiguous, but beginners can not understand what is the problem.
I think “potentially” is not needed as in design it is over copper so the warning is true.
I think silk over copper tells even beginners what is the problem but silk over mask opening need a while to associate the facts and not sure if it is easy for beginner.
Likewise for many other error messages…
That’s not necessarily true, if the mask layer is used for example for artwork. Usually an opening exposes copper, but not always.
Perhaps Silk over exposed copper would be clearer about the problem.
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Some people try to get the term “legend” to replace “Silk”.
That is misleading, at least for me. Silkscreen can and often should be over Cu, but not over exposed Cu. Silkscreen over soldermask opening is also not an error, and shouldn’t be, as long as there is no Cu in the same region.
This means the following error messages are wrong or misleading:
- Silkscreen clipped by solder mask
- Copper clipped by silk screen
- Silkscreen clipped by soldermask opening
- Silkscreen removed in soldermask opening (dangerous, since it can lead to Silkscreen on exposed PCB pads while message would indicate otherwise)
- silk screen overlaps mask opening
- silk over copper
As @Dennisch suggest, “Silkscreen over exposed copper” is, as far as i understand, correct and not misleading.
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