Filled zone not connecting

[Rahul_Pillai]

I am pretty new to PCB designing and am trying to make a filled zone for my 4-layer PCB. I want layer 2 to be GND, Layer 3 to be 1V8, and layer 4 to be GND. My polygon is not making the final connection to make it a complete polygon and hence I am unable to fill any zones. Could someone pls help me with this, I have attached a picture for your reference.

Please do give me any tips you think may be relevant

[paulvdh]

1. Don’t use: PCB Editor / Place / Draw Graphic Polygon [Shift + Ctrl + P] As it’s name implies it is a mainly graphical object. It is possible to assign a net name to it (in newer KiCad versions). But that is not it’s intended use.
2. Do use: PCB Editor / Place / Add Filled Zone. At the moment you click the first point on the canvas to start drawing it’s outline, KiCad shows it’s zone properties. You have to select a net name here to connect the zone to that net.
3. Occasionally press the b key to recalculate internal zone geometry. KiCad then creates pad connections (solid, none, thermal reliefs) according to KiCad’s settings, and it keeps defined clearances from other items.

Also note, that if your zone is on an internal layer, you can only connect to it through via’s.

[teletypeguy]

Hi and welcome to the kicad forum! For someone new to pcb design your board looks very nice.

Perhaps your edge cut and zones are not defined properly. Here I put a circle on the edge cut layer to define pcb perimeter:

Now I select layer 2 and select the filled-zone tool. Probably does not matter what starting layer selection is as the check boxes on the left of the dialog let me select layers 2 and 4 for this ground zone. Be sure to select the correct net:

Now I draw a random closed polygon outside the edge cut boundary:

Press B to fill zone(s).

I have copper going to the edge, which is very bad form, so go into board setup and add some clearance:

And then B again:

You will need another polygon for your layer 3 power plane, done the same way but selecting the appropriate net and layer.

[paulvdh]

For others reading this:

@teletypeguy

I have copper going to the edge, which is very bad form,

Indeed. This was the default for some time, and this has been solved. Now (V8.0.4) the default is 0.5mm. I verified this with:

1. Exit KiCad.
2. Open KiCad’s configuration directory.
3. Rename the “8.0” directory (for example to asdf_8.0)
4. Start KiCad, (KiCad asks all the questions again you get after a fresh install).
5. Create new project.
6. Open PCB editor and observe this Copper to edge clearance.
7. Exit KiCad.
8. Delete the 8.0 directory.
9. Rename the asdf_8.0 back to 8.0

KiCad’s defaults are only generated once for each mayor KiCad version, and settings from older versions can also be migrated. With the renaming trick above you can create multiple configurations and also use a program like for example meldmerge to compare and copy individual settings between such configuration directories. It’s all human readable text and pretty much self explanatory.

[Rahul_Pillai]

Thank you for your reply Paul. Could you tell me more about how to fill zones on my internal layer and connect it through vias? For example if I want to power the 3rd layer (internal) with 1V8, would it be good to have multiple vias coming from the 1v8 pad of my 3v3 to 1v8 voltage regulator?

[Rahul_Pillai]

Thank you teletypeguy! This fixed it.

[paulvdh]

I usually draw the zone itself as an irregular pentagon around the PCB. This makes it immediately clear if there is some problem with Edge.Cuts and this does not properly clip the zone. There is also the issue with PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to edge clearance. This was set to zero by default for some time, but copper should never extend to the edge to the PCB. At the moment the default is a sensible 0.5mm, but this number is in KiCad’s configuration directory, and when that was generated when this was set to 0, it probably still is zero for all new projects.

For connecting with via’s. You just have to place the via’s (either with the standalone via tool or during routing of tracks. All normal via’s punch through all PCB copper layers as an inherent result of how PCB’s are manufactured. When you hit the b hotkey to re-calculate internal zone geometry, KiCad takes care of the rest. It connects to vias of the same net, while it also creates a clearance to all other nets. To preserve as much of the integrity of the GND zone, space via’s of other nets a bit apart. Small groups (3 or 4) are OK, but do not make long rows of via’s that create big interruptions of the GND zone.

I tend to use two via’s for pads that connect to the GND zone. For QFP packages for example one just outside the pad, and one under the IC. But I am not sure whether this is actually better then a single via.

Don’t make via’s too small. Small drills are fragile and break easily, and thus the machines have to be more careful (slower) which costs money. A rule of thumb is to use at least one via for each (half?) amp of current. Too few via’s and they will start acting as fuses (just as too narrow PCB tracks). But such things also vary with copper thickness and via diameter.

Also, dedicating a whole layer to an 1.8V (or any other) power rail is wasteful. On 4 layer PCB’s it is quite common to assign both internal layers to GND, but keep at least one of them as a complete GND zone (except for via holes). the other is then often combined with routing some tracks. GND zones are important, power distribution is much less critical, and mostly relies on local decoupling capacitors for the high frequency part of the DC delivery

Rick Hartley made an excellent 2 hour and 19 minute youtube video about the importance of good GND zones. And the video is worth watching at least twice (with a few months in between). That is how important GND zones are. Rick Hartley is also a good talker. Pleasant to listen too, while also keeping to the point, and not “building suspense” for most of the time as many other youtubers do to fill the video and make it as long as possible.