Fill zone behavior

Hi
My apologies if this Topic has been addressed elsewhere in the forum. I am new to KiCAD and have been using Altium/ SolidWorks PCB for most design work. I am giving KiCAD a shot for personal project use after some frustrations with Flux.ai.
I am trying to use the filled zone but getting unexpected results and can’t seem to figure out why.
Snap shot below shows the filled zone.


The blue arrows point to the outline of the zone I created. What I don’t understand and can’t figure out is why the zone shrinks in certain areas ( yellow arrows) especiallly around the pads. I have played around with the settings / properties of both the pads and the zone but can’t seem to get it to fill all along the defined outline
Anyhelp will be most appreciated

are there keepout zones layers regions etc defined on those components ?

also Look carefully through all the rules- the board setup- design rules- constraints, and custom rules.
What KICad version ?

-glen (heavy Altium user)

To me it looks like there is a keepout zone under each of the footprints.

Hi glenenglish. Thanks for the response. The components were imported from Ultra LIbrarian online to create the footprints. I will check footprints again to see if I am missing anything in terms of keepout regions. They may be on one of the layers I am missing. Thanks for the pointers

KiApplication: KiCad x64 on x64

Version: 7.0.10, release build

Libraries:
wxWidgets 3.2.4
FreeType 2.12.1
HarfBuzz 8.2.1
FontConfig 2.14.2
libcurl/8.4.0-DEV Schannel zlib/1.3

Platform: Windows 10 (build 19045), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:
Date: Dec 28 2023 21:18:15
wxWidgets: 3.2.4 (wchar_t,wx containers)
Boost: 1.83.0
OCC: 7.7.1
Curl: 8.4.0-DEV
ngspice: 41
Compiler: Visual C++ 1936 without C++ ABI

Build settings:
KICAD_SPICE=ON
CAD version below

Hi paulvdh,
Glenenglish suggested same. so I will go back and check those components to see. It may be that most components from Ultra Librarian come with a keepout zone somwhere that I am not seeing.
Thanks for the pointer

This is the zone Paul and Glen are talking about . . .

ustireman, when you get enough posts accumulated, you can attach a file ie pcb or pcb and library footprint etc we can take a look.
so (never done this)
I read the doco (yes paul -I know amazing) about keepouts in kicad , they are called rule areas… then went into footprint editor and added a “rule area” on top layer
image
see the region under the component- the wonky tall rectangle
image
before:
image
after I inserted the KO :
and Voila !
image

so maybe you have a keepout (“kicad : RULE AREA”)
OR maybe the tool has imported the courtyard as a rule area ?

Guys,
Thanks so much for the pointers. I went back and looked based on your feedback and found the so called KiCAD rule area on the foot prints in question. I was looking for keepout initially and not rule areas. It did the trick. Most appreciated. I will have to go through all the footprints I downloaded and remove those rule areas


id the magic for me below is the repoured region with expected behavior

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I’m an altium person so I get it. I will eventually write a document "Kicad for die-hard Altium users’

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You find all sorts of interesting and frustrating stuff in the auto-generated footprints from UL & other similar sources. For me they are not worth the time and effort.

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I don’t understand why you appear to have more trust in sources such as Ultra librarian then in KiCad’s native libraries. A few years ago I was surprised and slightly annoyed by the sudden appearance of rounded corners for pads in KiCad, but that lasted for only a short while. After I read some of the reasons for doing this, I was impressed in the quick adoption of this improvement in KiCad’s libraries.

I’d say dont trust any one else’s librarys. use them as a guide or a starter, for sure.
The mfr: "CAD ready file " footprints - (not just a datahseet recommend footprint) - They’re useful if you cant reconcile the mechanical drawing to your complete satisfaction.

All my pads are rounded , and all my stencil apertures are rounded (differently)

Hi Paul I understand. KiCAD did not have the particular footprint for the Inductor in their native library. . Unless its an exotic part like some of the RF stuff I sometimes deal with I find that most of the online sources from Component search engine and Ultra librarian are “good enough” not perfect but good enough. This is my second week of using KiCAD and for the time being don’t need to go through the hussle of footprint creation from scratch while getting used to the interface.

I never create footpints from scratch. I copy KiCad footprint into my library and modify it a little. Footprints are files so I copy them using my file manager. I don’t have KiCad libraries on my library list so I don’t see the KiCad footprints. Practically I copy a group (based on file names) of footprints (= files) into my library (=directory) and then look at them and delete all except the one I select to use (after little modifications).

You copy something like and based on datasheet you modify pads (double click) and graphic lines at Fab, and Courtyard layers.

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Rule area (keepout) under power inductors are not completely meaningless. There should be no GND zone under fast switching pad. See how that pad looks in your inductor - it frequently is also close to PCB surface over the region between footprint pads.
If your SW net is switching than I would not do it as a zone. I would try to have the EM emitting surface be as small as possible.

Not always true Piotr. I usually avoid too much copper pour under inductors to avoid shorts, soome of those inductors have metalization under them.

You write in the way that I don’t understand.
You start with “Not always true” but then it looks that you write the same as me.

I’m only not sure about that fragment of metalization under them. Do such metalization suggest to use copper zone under inductors? If yes than that could explain “not always true” but I don’t know what kind of metalization do you mean.

sorry. English language has some ‘double- negative’ phrases.
I mean to say , sometimes you want ground under high speed pads. Sometimes the capacitance is useful. sometimes it might form part of a transmission line. Sometimes you do not want that parasitic capacitance. sometimes you do. Sometimes you want the capacitance to ground to reduce EMI for example, or to use as a ES shield.

OR you might want to use a ground pour under the inductor to electrostatically shield (ES) traces underneath the inductor on other layers- lots of reasons to use ground under SMPS inductors.

design dependent.

I don’t use zone on top under SMPS inductors, but I have 100% GND zone at bottom.
I have written that “Rule area (keepout) under power inductors are not completely meaningless.”
Not sure if I wrote exactly what I wanted to say. I wanted to say that they can have some sense for someone. I assumed that these rule area excluded zone only at top layer (I believe that when inductor flipped it will also be flipped to bottom, but never used any rule area in footprint).

If the rule area is contained as part of the PCB footprint, I’d expect it to layer flip correctly. I wonder if it does.
For things like 2520 HV capacitors, I put keepouts on the component in the library. . For inductors usually I do that manually at time of board route.