Fedevel iMX6Rex Module(SOM) migrated to KiCad

Hi All!

I hope somebody will find it useful, I migrated openRex imx6 SOM to KiCad. That’s an open source ARM SOM module from Fedevel courses. You can find it in my gitlab:

The course I just finished is an Advanced PCB Layout Course.
(Link removed by mod)

That’s a really nice one and I would recommend it.

I hope Robert Feranec, the author, will create a course based on KiCad as well someday.

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Very interesting!

I’m curious: did you have any issues in performing any of the advanced layout techniques in KiCad?

I haven’t done any advanced layout course myself but just learned along the way. To me KiCad seems to have everything you need to do advanced layout. Maybe the only thing is EMC / crosstalk simulation which requires a bit of manual effort through OpenEMS.

Hi Qbort,
I never performed any advanced PCB layout in the KiCad yet. I just migrated SOM module t and want to proceed with courses tasks in the KiCad then. I would presume some troubles:
a) depends on your stackup, you will need to have tracks and differential pairs with different parameters on different layers to mach the target impedance.
b) Robert from Fedevel suggests to make some bigger differential pairs to occupy PCB space and later on change its parameters. I’m not quite sure, if that can be done easily in KiCad.
maybe some more…
I think it will be the most annoying parts. Of course, you can write python scripts to help with that…

Hi

For the record, I used the current nightly build (Version: (5.99.0-3375-ge137d61b29), release build) to open this nice project. After refilling the zones, KiCad exhibits 13 unconnected nets, and when doing a DRC, it crashes. As I don’t really know the status of this project (WIP ?), I’m hesitating to write a bug report.

I’m not sure what project you refer to, but if any design, schematic, layout, footprint or symbol has been designed with KiCad (without external tools), either with 5.99 or an earlier version, KiCad shouldn’t crash when doing something with it. Actually KiCad shouldn’t crash even with malformed input.

If the “project” means that openRex in gitlab which was linked to, it has been imported using KiCad’s internal features AFAIK, and any bugs caused by it are bugs in KiCad, either in the Altium importer or somewhere else.

I cannot see any unconnected nets when polygons are filled. That project is from the Fedevel academy and it is active, you can even buy that iMX6rex modules. My target was to migrate to KiCad so anybody can practice, do lessons or study high-speed design without Altium (if that’s possible). My DRC shows only courtyards overlaps in few places, so pretty much project should be alright. I see that DRC crush on very last KiCad builds. But for sure it belongs to some KiCad nightlies bugs.

Eeli, indeed I see that KiCad crash during DRC
assert “Assert failure” failed in Create(): Unknown DRC error code
Do I try to localize that and make a bug report to KiCad? Will it help? Or it is better to write bug reports only with releases?

I used Altium2KiCad perl scripts. I just realized that there should be some internal importer but for some reason I cannot see it in my build O_o
Anyway, in some older nightlies this project was fine.

Definitely all bugs should be reported before they have been released! :slight_smile:

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It works only in standalone Pcbnew because KiCad doesn’t support Altium projects or schematics (yet).

I confirm with the very last nighlty build available (Version: (5.99.0-3389-ge8d09cd998), release build)

IMHO, the best way would be to try to reimport it with a recent build by using the built-in importer and check if the result is the same after re-filling all zones (“B”).

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Hi, but I’m sure on the picture you sent, there are no polygons filled. In that case you suppose to have unconnected nets.
I imported board with internal KiCad tool and it still crush. I will try to look for simple layout which will still generate that bug and create the bug report.
Maybe later on I will change the pcb file for new one (generated by kicad tool), but there will be hundred of components which will have wrong arrangement after linkage between pcb and schematic.

My nightly build keeps crashing even with 1 single microvia.
There’s the bug report

Thanks for sharing! I want to start this course using KiCad and it will help me!

You are welcome!
You will probably have some troubles once you will start the length matching.
By the way, do anybody know, are there some tools to length match netclass? It’s probably not a big deal to make a handy python script for that…
I think to write down all features I need to do proper high speed layout. Maybe it’s already implemented in some scripts or devs doing that.