Hi all… I have an idea for an alternative method of dealing with subcircuits (hierarchical sheets). I used to work at a startup for similar style software (though it focused on analog IC design), they had a rather nice way of dealing with hierarchy.
Design a circuit, add the hierarchy pins. Then create a symbol for the circuit, syncing the pins in the symbol with the ones in schematic. Add that to the library (project library or a global library?)
When you need the circuit in a new project, you can instantiate it, giving it a name starting with I (for “Instance”). Or whatever letter you wish. Then when netlisting you can use that name. Netlisting nets inside the subcircuit would have a name prefaced with the instance name. For example, if the subcircuit has a net named “BOB”, and there are two instances of the subcircuit, there would be two net, I1/BOB and I2/BOB. Also, for nets connected to pins, we’ll always use the shortest path name (because they really have two names for the same net. So if the main sch has ALICE as a net that connects to a pin (BOB) in the subcircuit, it would be referred to as ALICE in the netlisting (even though it could be referenced as I1/BOB). I suspect we’re already doing similar already with sheets. And you would do the same type if naming with the parts/circuits in the subcircuit. I2/I4/C7.
Any thoughts? If folks like it, I’ll add it as a feature request in Gitlab.