Fab thinks board has short circuits, but it passes DRC

I am trying a new fab (Elecrow), and they emailed me and said my board has short circuits. They attached this image:

But my board passes DRC, and also I had fabbed an extremely similar (though slightly different) version of the board previously with another fab, and it works. And since Elecrow does not have the netlist, just the Gerbers, I’m not sure how they can tell what is a short anyway?

It looks like most of what they are highlighting are cases where a track is redundant with a filled zone. (Wouldn’t this be fairly common, though? Am I doing something unusual here?) There are a couple of places where I am doing something unusual: I added redundant tracks in an attempt to anchor some pads, because I’d had trouble with them delaminating in an earlier version.

I’m tempted to just tell them that it is correct and they should fab it anyway. But is there anything I should beware of? Am I doing something I shouldn’t be doing? Does anyone recognize the tool they’re using to find these “shorts”?


Did you intended to have these strange traces connected to the pads that are pointed out? They look kinda wacky to me, not necessarily shorts though. Although small enclosed spaces are best avoided to make sure no funny under etching occurs.

The two pads I’ve circled in red below are the pads where I added redundant tracks to try to prevent delamination. Admittedly this is weird and inelegant; is there a more accepted way to prevent pads from peeling off when I try to desolder them?

All of the other arrows are pointing at my GND fill. I connected all of my GND pads with tracks, to make sure they are fully connected. Then I added a filled zone. Is there a different way I should do this? Or is KiCad doing something weird when it adds the GND fill?

The larger area area looks like a fill polyline that did not fill ? - not a short, but certainly ‘strange’
The smaller red area is unusual routing, also not a short, but also ‘strange’.
There are many other ‘strange’ areas where it looks like your GND fill polygon was made complex, to almost, but not quite follow the traces.
You may also have the GND fill-PAD clearance much larger than the trace-pad, which means the fill rule reaches past the trace and pushes the fill area on the other side of the trace away - gives a small void.

Usually, you keep the fill outlines simpler, and just use the clearance rules to pull back from traces.

There are a couple of places where I am doing something unusual: I added redundant tracks in an attempt to anchor some pads, because I’d had trouble with them delaminating in an earlier version.

Use larger pads, or a pour area, or use a temperature controlled iron, & more care …

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That was just me drawing extra tracks to try to anchor the pads:

The GND fill was as simple as I could make it, while still staying inside the board outline. The GND fill is the red hatched area below:

Yes, I left the fill clearance set at the default, which appears to be 20 mil. Should I have made it smaller?

Your layout is certainly bizarre, as a fab I would definitely want the customer “signing off” on that before I made it.

You don’t need all those redundant tracks that connect the pads that are otherwise connected by the copper zones, especially since many of the tracks are outside of the zones. The remaining redundant tracks you say are to “prevent delamination” are a bit of a mess regardless of their purpose. Why do that to some pads but not others? Those pads are more prone to desoldering? I think they are more trouble than they are worth especially as they are at the moment. Clean the board up and you probably won’t have any issues. If delamination during desoldering is a problem then improve the desoldering techniques used.

So you would recommend filling the zone first, and then only adding tracks in the places where the zone isn’t fully connected?

Yes, fill the zone, which DRC does anyway, and if you can’t adjust things so that the zones connect to all pads then make any remaining connections with tracks.


I’m interested in why the fab flagged it, as you say without netlist how do they know? But then if they do e-test as some claim, then they would need to regenerate a partial netlist from the Gerbers. Maybe it got confused by tracks that appear to loop back on themself.

I wondered if it might be a track-track clearance issue, but that doesn’t seem to be consistent with the arrows.

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As long as the zone is connected to a net I think it will be contained by the edge cuts. At least that’s the way it works in the nightly I’m using and I think remembering it that way in 4.0.debian ancient kludge.

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I’m sure they could generate a netlist that would correspond with the gerbers but in the case of two shorted nets it would simply treat them as one net. I suspect this didn’t pass the initial visual inspection. I’m sure the op could simply declare there is no short and ask them to proceed with manufacturing if he really wanted to.

Thanks, that’s good to know. I’d just been operating under the assumption that KiCad ignores Edge.Cuts, because I know that the interactive router will happily route tracks across Edge.Cuts. (Which gets very annoying with an oddly-shaped board like this.)

What you said about interactive routing is true, at least up to a year ago . . . perhaps it gets improved in Ver 5. But (like @hermit said) the “Fill” algorithm does a good job of honoring Edge.Cuts, at least it does so if your Edge.Cuts define a closed polygon.

KiCAD’s “Fill” algorithm seems to treat an Edge.Cut line as if it was a trace. This means it will leave a gap equal to the zone’s “Clearance” parameter between the edge-cut line, and the filled zone. See the screenshot attached to my post at Creating “zone outlines” for Odd Shaped PCB’s . The clearance is to the EDGE of the line-width of the drawn edge.cuts line - same as it does for tracks. So if you want a larger gap to the edge of the board vs. the zone’s clearance to other parts of your design (tracks, vias, etc) just modify the edge.cuts line width. A thicker line will cause a larger gap towards the edge of the board. (Every modern board manufacturer defines the CENTER of the edge.cuts line as the edge of the board.)



In that post, I don’t understand why you recommend exporting and importing the Edge.Cuts as a DXF. If filled zones honor the Edge.Cuts, couldn’t I just draw a bounding rectangle around my entire board?

I’d use a fill area for that, or make the pad itself larger.
Was the lifting issue during assembly, or in use ?

Yes, or make the GND traces larger, to remove the slit effects everywhere.

I had a board with a bad pot, so I desoldered the pot using some Chip Quik. In so doing, one of the pads for the pot pulled off, hanging just by the tiny track attached to it. I figured that by adding more tracks I would give it more to hang on with. It takes me about an hour to solder one of these boards, so I don’t want to have to throw out a board just because I messed up desoldering a bad component.

(In practice, the pot is the only one of the SMT components I’ve had to desolder. I’ve never had a problem with the SMT resistors and capacitors. And although I’ve had to desolder some LEDs, they are THT and don’t seem to have as much trouble with delamination.)

I’d originally been following @dchisholm’s advice from the Turn off GND airwires thread:

Both approaches are valid - if you rely on fill connecting, you do have to ensure you run DRC before plotting !!

If your fill clearance is larger than trace clearances, and your board is denser, you can find fill does not reach all pads.
In this case, manually running GND traces makes sense, and also remind you to leave room…

Nightly interactive routing has understood the edge.cuts and keep outs for a month or so.

One thing to watch for is that Pcbnew Netlist import defaults to “keep tracks joining two nets”, raising the possibilty of there actually being a short

But wouldn’t DRC catch this?