Thanks for your answer,
I saw your post before I open this thread, because I’m not clear how to do that,
I tried many tools but none of them works for me,
I don’t know why we must use the STEP format,
why we lost tracks and pads when using StepUp,
why the photo and video posted by you don’t lose tracks and pads,
what do you do for those castellated pads before rendering?
I try to open my board from StepUp, I got many errors and warnings, and an empty board at end:
(maybe I use the latest KiCad version from Git repository)
Logs:
duke@duke-uf /mnt/TT/SA/kicad-git/demo $ freecad kicad-StepUp-tools.FCMacro
FreeCAD 0.17, Libs: 0.17R10047 (Git)
© Juergen Riegel, Werner Mayer, Yorik van Havre 2001-2016
##### #### ### ####
# # # # # #
# ## #### #### # # # # #
#### # # # # # # # ##### # #
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# # # # # # # # # ## ## ##
# # #### #### ### # # #### ## ## ##
PoM not present
kicad StepUp version 5.0.2.7
tolerance on vertex applied
applying Materials to Shapes
your home path is /home/duke
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules
volume 0 heigh 0
bounding box option 0 whitelist
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
export to STEP True
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules
volume 0 heigh 0
bounding box option 0 whitelist
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
kicad StepUp version 5.0.2.7
tolerance on vertex applied
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules
volume 0 heigh 0
bounding box option 0 whitelist
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules
volume 0 heigh 0
bounding box option 0 whitelist
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
opening /mnt/TT/SA/fpga/cd485_pcb36/cd485.kicad_pcb
my file path /mnt/TT/SA/fpga/cd485_pcb36
FC Version 017
kicad_pcb version 20170123
PCBThickness0.4 mm
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
PCB Loader
2d closed path
max Length=5.5 index=0
running time: 0sec
start cutting
running time: 0sec
running time: 1sec
VBO status False
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
running time: 1sec
missing models
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
error: reset values of scale to (xyz 1 1 1)
exporting to MCAD
/mnt/TT/SA/fpga/cd485_pcb36/cd485.FCStd
Board Placed @ 0.0;0.0;0.0
kicad pcb pos: (57.750;-49.600;0.00)
running time: 4sec