Export to VRML, Holes and VIAs become hexagon, and pads lost

[dukelec]

I test it both on stable version and last commit from git.

I have to remove the part of pads which outside the board,
because I should post the picture to my product document,
I think it’s unacceptable even for a small DIY project,
can’t believe why this are acceptable by developers for such a long time.

I used to use a huge rectangle pad, which cut the pads on the edge.
and then got two different pictures with different problems by different render,
then import both picture to GIMP, use one as the mask, then remove the unwanted part of another one.

(I modify the code to remove the pad outside board for ray-tracing render, but sadly got the thinness black ring left).

(to be continued…)

[dukelec]

Then get the result picture at last:

This is very inconvenient for me, so I want to export the 3D files and render outside by blender, but I found that the copper of all pads are disappeared, and holes and vias become hexagon, and I can’t find a way to change the fragments setting.
(board size is 8.3 x 5.5mm)

(to be continued…)

[dukelec]

Render in blender:

(to be continued…)

[dukelec]

Same board render in KiCad:

(-- end --)

[cbernard]

One issue is that we never correctly trimmed features outside the board edge; it’s not as easy as it might sound and castellated edges are one of the rare situations where this matters. For the hexagonal vias within the VRML exporter, any holes smaller than a certain diameter are rendered as hexagons; larger holes are rendered with more segments according to a geomteric rule; I think it is set so the max. deviation from a true circle is 0,1mm. The VRML export code is very different from the 3D viewer code so you will always find differences between the rendered items between those two. Whether or not the VRML code is improved depends on whether or not someone puts in the time. I made improvements to the code many years ago because the result then was too ugly, but I was never really interested in that work because the only thing that matters for me is the 3D mechanical model. So - if you can find a programmer who is interested in improving that then there is some hope.

[kammutierspule]

@dukelec

I think it’s unacceptable even for a small DIY project,can’t believe why this are acceptable by developers for such a long time.

The developer, that took KiCad’s sourcecode and developed the 3D-Viewer followed only by his own interests, didn’t care about that issue. Do you care you about it?

KiCad 3D-Viewer (or others 3D viewers from other softwares, I suppose) is not considered a formal validation of a design, so its result does not matter too much.

[Rene_Poschl]

@maui might know a trick how to get it to blender. I seem to remember he posted some pictures some time ago.

@kammutierspule

KiCad 3D-Viewer (or others 3D viewers from other softwares, I suppose) is not considered a formal validation of a design, so its result does not matter too much.

It’s still damn good for that purpose. (It’s a lot easier to see problems with the silk screen in the 3d viewer than it is in pcb_new)

It also helps for finding collisions between larger parts. (Phoenix connectors for example. But only if you use 3d models that include the mating connector ;))

Don’t play down the capabilities it already has. It makes very nice renders (even better in nightly)

[maui]

@dukelec

Render in blender:

@Rene_Poschl

@maui might know a trick how to get it to blender. I seem to remember he posted some pictures some time ago.

no problem in Blender if you use the smoothing option

3D new library for Mechanical CAD exporting and enclosure design

I played a bit with Blender scripting thanks to @Joan_Sparky to point out the smoothing part of the rendering just an info: FreeCAD 0.16 stable has been released

@dukelec

and holes and vias become hexagon

This is a PEBCAK, not of kicad developers fault

[Rene_Poschl]

How did you get the castelions to look that good? (The original poster had problems with them.)

[maui]

The rendering in blender is obtained exporting a STEP model to wrl with StepUp and then imported in blender. This smoothing can solve the hexagonal prob…

Castellated pads are a bit tweaky in kicad… You can export your board and parts with StepUp to step and then to WRL… But you will miss tracks and pads

How to share step 3D model with all the components on the PCB too?

@kammutierspule here there is a fully Open Hardware KiCad project that @Anool did at Hackaday with all STEP and VRML models coming from @Anool, @Joan_Sparky, me and StepUp libraries https://sourceforge.net/projects/kicadstepup/files/prjs/HACK-master-R3.7z/download I updated the 3D VRML models adding Material Properties as per your Guide Lines [image] [image] hack-VRML.7z (272.8 KB) [image] hack-fused_FreeCAD-016.7z (780.7 KB) and the MCAD + VRML combination (mechanical model plus VR…

All other are work arounds

[maui]

@kammutierspule

The developer, that took KiCad’s sourcecode and developed the 3D-Viewer followed only by his own interests, didn’t care about that issue.

Hummm… not really… the developer of the 3D-viewer (you ) was so gentle to listen to me and other users and added many USEFUL features to the previous 3d-viewer that I couldn’t work without!!!
Many many thx @kammutierspule for your great work!
Maurice

[dukelec]

Thanks for your answer,
I saw your post before I open this thread, because I’m not clear how to do that,
I tried many tools but none of them works for me,

I don’t know why we must use the STEP format,
why we lost tracks and pads when using StepUp,
why the photo and video posted by you don’t lose tracks and pads,
what do you do for those castellated pads before rendering?

I try to open my board from StepUp, I got many errors and warnings, and an empty board at end:
(maybe I use the latest KiCad version from Git repository)

Logs:

duke@duke-uf /mnt/TT/SA/kicad-git/demo $ freecad kicad-StepUp-tools.FCMacro
FreeCAD 0.17, Libs: 0.17R10047 (Git)
© Juergen Riegel, Werner Mayer, Yorik van Havre 2001-2016
  #####                 ####  ###   ####  
  #                    #      # #   #   # 
  #     ##  #### ####  #     #   #  #   # 
  ####  # # #  # #  #  #     #####  #   # 
  #     #   #### ####  #    #     # #   # 
  #     #   #    #     #    #     # #   #  ##  ##  ##
  #     #   #### ####   ### #     # ####   ##  ##  ##

PoM not present
kicad StepUp version 5.0.2.7
tolerance on vertex applied
applying Materials to Shapes
your home path is /home/duke
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules 
volume 0 heigh 0
bounding box option 0 whitelist 
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path 
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse  #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
export to STEP True
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules 
volume 0 heigh 0
bounding box option 0 whitelist 
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path 
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse  #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
kicad StepUp version 5.0.2.7
tolerance on vertex applied
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules 
volume 0 heigh 0
bounding box option 0 whitelist 
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path 
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse  #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
ksu file 'ksu-config.ini' exists
materials section present
turntable section present
compound section present
docking section present
font section present
3D models prefix=
3D models prefix2=
pcb color=0.0,0.298,1.0,lightblue (0,76,255)
blacklist modules 
volume 0 heigh 0
bounding box option 0 whitelist 
placement board @ useBaseOrigin #place board @ 0,0,0
idf_to_origin True
last fp path 
last brd path /mnt/TT/SA/kicad-git/demo
virtual models noVirtual
export fusing option nofuse  #default
minimum drill size 0.0mm
export to STEP True
enable materials True
turntable True
compound allowed True
docking mode left
kicad StepUp version 5.0.2.7
opening /mnt/TT/SA/fpga/cd485_pcb36/cd485.kicad_pcb
my file path /mnt/TT/SA/fpga/cd485_pcb36
FC Version 017
kicad_pcb version 20170123
PCBThickness0.4 mm
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
wrong scale!!! set scale to (1 1 1)
wrong scale!!! for ${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl Set scale to (1 1 1)
PCB Loader 
2d closed path
max Length=5.5 index=0
running time: 0sec
start cutting
running time: 0sec
running time: 1sec
VBO status False
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl
model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.wrl
model name c_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.wrl
model name r_0201
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
running time: 1sec
missing models
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/r_0201.step
/mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/c_0201.step

${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/c_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
${KIPRJMOD}/dcdc.3dshapes/r_0201.wrl
 error: reset values of scale to (xyz 1 1 1)
exporting to MCAD
/mnt/TT/SA/fpga/cd485_pcb36/cd485.FCStd
Board Placed @ 0.0;0.0;0.0
kicad pcb pos: (57.750;-49.600;0.00)
running time: 4sec

[Rene_Poschl]

@dukelec

I try to open my board from StepUp, I got many errors and warnings, and an empty board at end:

You need to tell stepup where the step models or your footprints are located. If you use the official kicad 3d files, simply give it a pointer to the installation directory. Better still download the kicad-library repo (and point to the modules/packages3d subfolder) to get all models that have been added in the last few month. (4.0.6 has a lot fewer models than are on the official repo)

[maui]

@dukelec

I don’t know why we must use the STEP format

STEP is for mechanical design

@dukelec

why we lost tracks and pads when using StepUp

StepUp is aimed to make a conversion from ECAD design to MCAD design… only mechanical aspects are concerned by this conversion

[quote=“dukelec, post:12, topic:7224”]
why the photo and video posted by you don’t lose tracks and pads[/quote]
When you see my rendering in Blender, most of them are just WRL kicad exported imported in Blender, so StepUp is not involved in this part (not completely true: in fact I used StepUp to create the 3d parts with material props); anyway those rendering don’t have castellated pads… (the Module_AI-Thinkerer-ESP07 model is a 3d STEP model designed in MCAD by Joan that I converted to wrl by StepUp, but the model doesn’t have any tracks)

@dukelec

what do you do for those castellated pads before rendering?

using StepUp your board will have castellated edges as in the real pcb, but pads will not be converted

As I pointed out before, castellated pads is a feature not implemented in kicad rendering ATM, so for rendering purposes you need to make some workarounds that are not always simple to apply…

PS for the correct use of StepUp you need to configure the tools in the ‘ksu-config.ini’ file, assigning as Renè said, the prefix path to your 3D model library

[dukelec]

Models were made on my own, not from official repo,
The file xxx.wrl is exactly exist on the path.
StepUp check for xxx.step first, then roll-back to xxx.wrl.

model name WLCSP36
error missing /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.step
${KIPRJMOD}/dcdc.3dshapes/WLCSP36.wrl
adjusting Relative Path
step-module-replaced /mnt/TT/SA/fpga/cd485_pcb36/dcdc.3dshapes/WLCSP36.wrl

I’m not good at blender and other CAD tools, I think something like openjscad is more kindness for me,
I thought I can cut unwanted parts of castellated pads though it,
or maybe I should spend more time to learn blender, and just erase things in blender.

I tried to modify some code in VRML exporter few month ago,
but I give up because I found that’s a huge work,
and maybe rewrite it in python is much easier.

I don’t have time for it at now, I’m gonna use the old method mentioned at top,
Maybe next time VRML exporter has already improved by someone,
or that’s time to start the job by me otherwise.