Hi, I have a trace from the GND pin on my IC (ATTiny84) to the - end of a decoupling capacitor, and I do not want that trace to be part of the ground plane when I fill it. How can I do this?
Before fill:
After the fill it connects both the capacitor end and the GND pin to the ground plane
Thanks!
You can draw a keepout area around that trace. But what’s the point of a ground plane if you don’t want it to connect to ground?
Alternatively you can use a net tie to create a new net with just the GND pin of the ATTiny and the decoupling cap.
Sometimes it’s beneficiary to keep the GND plain free of noise, and one of the ways to (apparently) do this, is to have the decoupling capacitors as close as possible to the IC’s (as usual), then a PCB track of around 15mm, and only then connect it to the GND plane.
The idea is that the 15mm track has a little bit of inductance and this forms a low pass filter with the decoupling capacitor.
[Edit]
After qu1ck’s post I tried to get some more info on this, but failed. From memory, the example was a 4 layer board with a continuous GND plane (except for via’s poking through) I also do not have much experience with real high speed design and signal integrity. When searching for the article I did happen to gather together some particularly nice magic words:
https://duckduckgo.com/html?q=high+speed+pcb+design+clean+gnd+plane
which finds stuff like:
https://www.emcstandards.co.uk/files/pcb_layout_techniques_for_low-cost_emc_iee_review_august__october_1999_1.pdf
https://www.utwente.nl/en/eemcs/te/education/emc-demonstration-boards/emc-europe-brugge-2013.pdf
https://edg.uchicago.edu/~tang/ATLAS_SCT/an224.pdf
Is there actual math behind that or is that just a myth like right angle traces?
Because it seems to me that any potential benefits of that tiny low pass filter will be negated by the loop antenna created by cut up ground plane and power traces. I’m not an EE though, so ¯\_(ツ)_/¯
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