Exclude track from copper filled zone

[gschelotto]

Is it possible with kicad? I have obtained this gerber layout from a high power DC/DC converter. There is a track (GND) that is not part of the copper zone (GND). The idea is to trace a signal return that is not in contact with some part of the plane, despite the fact that it is the same net.

[Jonathan_Haas]

Either use a different net for the track (might need a net tie or two) or carefully place a no fill rule area around the track. Or modify the GND fill area so that it doesn’t overlaps the track (might need to split it in two).

[albin]

I would use a net tie. Search this forum to get better understanding. It’s basically a footprint which lets you connect two different nets together. There are several such footprints in the standard libraries.

[gschelotto]

Thank you. Apparently it is not a trivial subject. In my case I need a net-tie on one of the inner layers and this seems to be not resolved in kicad 6. I still don’t know how to do it.

[albin]

I see. I don’t think that it’s possible to use net ties on inner layers but I know that it’s been asked multiple times before so there might be some good ideas in the threads that exists. One solution would be the one suggested by Jonathan above, namely to place a no fill rule area around the track, or modify the GND fill area so that it doesn’t overlaps the track.

[der.ule]

It is not trivial but not that complicated either, you will need to edit the PCB file with a text editor and change the net-tie layer there:

Open your board file with a text editor (after making backup, etc. etc.) and look for your net-tie (find: “NetTie”)

  (footprint "NetTie:NetTie-2_SMD_Pad0.5mm" (layer "F.Cu")
    (tedit 5A1CF6D3) (tstamp 7e72019f-70d6-4200-8d40-91cc06eaa854)
    (at 74.6 40.3)
    (descr "Net tie, 2 pin, 0.5mm square SMD pads")
    (tags "net tie")
    (attr exclude_from_pos_files exclude_from_bom)
    (fp_text reference "REF**" (at 0 -1.2) (layer "F.SilkS")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp d17cd3e0-c500-4979-8a3d-513dab584ba7)
    )
    (fp_text value "NetTie-2_SMD_Pad0.5mm" (at 0 1.2) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 59276dce-6fac-432f-820e-7d5624ee650e)
    )
    (fp_poly (pts
        (xy -0.5 -0.25)
        (xy 0.5 -0.25)
        (xy 0.5 0.25)
        (xy -0.5 0.25)
      ) (layer "F.Cu") (width 0) (fill solid) (tstamp 44fb9d26-6be7-4af9-9b52-727c6d2c2acb))
    (fp_line (start 1 -0.5) (end -1 -0.5) (layer "F.CrtYd") (width 0.05) (tstamp 09c50095-4a68-4744-843b-92723b109ef5))
    (fp_line (start -1 -0.5) (end -1 0.5) (layer "F.CrtYd") (width 0.05) (tstamp 89e97db0-5f4a-4dde-aeae-e86434b6dba7))
    (fp_line (start -1 0.5) (end 1 0.5) (layer "F.CrtYd") (width 0.05) (tstamp d848cf6f-0548-4016-bba4-ddea192c9789))
    (fp_line (start 1 0.5) (end 1 -0.5) (layer "F.CrtYd") (width 0.05) (tstamp eb53b8c9-78a1-432c-8f40-c2413a3f0be5))
    (pad "1" smd circle locked (at -0.5 0) (size 0.5 0.5) (layers "F.Cu") (tstamp 5e04086f-f5be-4fa1-9077-58822adcbe80))
    (pad "2" smd circle locked (at 0.5 0) (size 0.5 0.5) (layers "F.Cu") (tstamp 904edd67-bb0e-43ec-aab9-09bb8c3ed308))
  )

Change all “F.Cu” to the desired layer (in this case “In1.Cu”):

NetTie in In1.Cu:

[gschelotto]

I really like this solution for inner layers.
It is not necessary to modify the PCB file. Just modifying the footprint is enough.