It’s a SMD pad (no net) connected with pin 5, 6, 7 and 8 (drain) of a TDSON-8-1 MOSFET.
BTW the latest kicad TDSON-8-1 footprint came with 5 pins (1 gate, 3 source and 1 drain) but I’d like to be aligned with the symbol and datasheet that have 8 pins (1 gate, 3 source and 4 drain)
I just wondered why it’s green, I don’t have that color in v6 color scheme. But actually it means that it’s the reason for the violation. You can’t connect or overlap pads with no net to pads with a net.
Yes, the green color indicates the violation.
Understood but how should I do in this case? I need a big thermal pad connected with the other ones.
If you want to retain the existing pin/pad numbering exactly as it is, you probably have to add one more pin with a number and give that number to the extra pad, then connect the pin to the same net.
There are other possibilities, for example giving all the pads the same “number”, for example “5…8”. It works because the pin number doesn’t need to be a number. Then you can have only one pin for them in the symbol and give it the same number. It doesn’t have so many pins but still retains the numbering visually.
Thanks eelik, I will explore both options but I’d opt for the second one in order to take advantage of the footprint provided by latest kicad library.
Is that “Green SMD” pad part of the footprint?
The most common way to connect pads in the footprint itself is to give them all the same pin number. Extensive use is made of this in for example all footprints with thermal pads (and via’s)
Does your DRC violation go away when you remove that green thing?
This is at least an easy wat to diagnose if that is causing the issue.
For further diagnosis, you can also upload a small example project with that footprint and a few nets to connect it to something else (for example different pins of a connector).
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Yes
Okay, I’ve modified the footprint as you suggested. All drain pins have the same number (5). Here’s the new symbol and footprint
Yes, the DRC violation is gone away.
Understood. Thank you for your help!
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Just a note, that you do not need to have bunch of 555 pins in symbol, only one will be ok.
I know but I’d like to be coherent with the real component as much as possible
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I know but I’d like to be coherent with the real component as much as possible
But to put 4times a “5”-pin into the symbol is the false way.
If you really want to be coherent:
- use a footprint with the pins 5+6+7+8+9 (or exposed pad as EP)
- and combine that with a symbol with Pins numbered 5+6+7+8+9 (or EP)
If you want it easy take the approach with:
- footprint with many “5”-Pads
- symbol with one Pin numbered “5”
The Footprint-editor + Symbol-Editor both have the main menu-bar-entry Inspect–> SymbolChecker / Footprint Checker. You should run this test on any new created/modified symbol/footprint to prevent easy mistakes. (and multiple pins with same pin-number are regarded as error)
I would go with this, but if keeping the correspondence with the datasheet pin numbering is wanted, I would give the pin number 5..8 to that one pin and pad(s).
BTW, it’s not necessary to have several pads; you can create one custom pad which is shaped like 5…9 pads together. But several pads is probably easier, especially if you already have the footprint with the pads.
While we are at it: How would you create a “footprint” for connecting two different nets (net names)? So two pins on the schematic symbol - and as little as possible Cu in the footprint (ideally no Cu)?
The DRC around this has changed in KiCAD 6.
Have a look for ‘Net Ties’ - there are symbols and footprints in the standard libraries. You need the keyword "NetTie’ in the description for these to work.
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Thanks. Suppose you make a small one like this - how do you route to it? Do you still need the clearance to the “other” pad? Is there a way around that?
Here pads are .1mm and traces are .3mm.
Also, no way to make this an inner-layer-only feature?
I’ve never tried to make one that small - I guess clearance should be between both nets - is there any reason why a longer tie is a problem?
Putting ties on inner zones is discussed here
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Ideally, a net-tie is a single point not taking up space. With this concept, you have to make different footprints for different Cu-to-Cu spacing rules set for the board + two vias to get to a surface layer if not already there. Odd, but hey… can work when in a pinch. Thanks.
You’re right. I’ve modified the symbol and footrpint this way
- There are 9 pads placed in footprint
- Pin9 (EP) Is not visible in symbol
- Pad9 is in touch with 5, 6, 7, 8 but not overlapped
BTW overlapping a numbered with a unnumbered pad does not detected by the Footprint Checker. But it is marked as a violation in a DRC.
The schematic represents an abstraction of the design and should be as uncluttered as possible. Adding all these extra pins makes it look quite messy in my opinion and doesn’t help clarify the design intent. You could stack these pins on top of each other which will have the same effect but look much neater. If you are wanting this information to help with any faultfinding later, I would personally make a note on another layer about the commoned pins and the ep.
Interesting point of view. On the one hand I agree on schematic abstraction but on the other I also like to observe a transistor with all the pins present in the datasheet so getting a first impression about its dimensions, thermal characteristics, etc just in an instant.
I think it’s a matter of taste. All the options seem valid to me.
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