Every Connection Track Too Close To Pad

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1

Hi All, I’m a newbie in KiCad working on my first two layer board. I’m getting a “Track Too Close To Pad” error in DRC on every single connection except ground. I must be doing something horribly wrong, because Google was no help.

If it matters, I’m etching my own board, so I’m using thick 1.5 mm traces. The board works, and I have no errors other than the “track too close to pad”. While a few pads had remnants of old traces, cleaning those up did no good. Every connection still has an error.

Any hints would be greatly appreciated. Thanks!

Screen Shot 2020-09-11 at 9.58.12 PM
Screen Shot 2020-09-11 at 9.58.12 PM1060×1024 22 KB

2

It would help if you can share your project. Hard to say what’s wrong just by looking at a screenshot.

3

It’s not in “… every single connection”, there are a few which have no error arrows:
image

You are also not: " doing something horribly wrong" It’s very likely some simple issue that you’re not aware of as a “newbie” yet. No worries.

First thing to do is to make the clearances visible. You can do that with:
Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outlines (*) Show Always

Can you recall how you got into this situation?
Normally KiCad does not let you draw tracks with DRC violations. It seems likely that you first drew the PCB, and then made the tracks wider.

To fix this, you may want to look into the workings of:
Pcbnew / File / Board Setup / Design Rules / Net Classes
but do note that this only sets the rules, and does not actually change anything on the PCB. That is a separate step, which can be done in different ways. One way is with:
Pcbnew / Edit / Edit Track and Via Properties

There are also more local ways to work with selections to change widht and clearance values, down to single track segments.

1 Like
4

Thanks for the suggestions! I tried showing clearance outlines, but there were no obvious issues. Deleting the traces and re-drawing also didn’t help.

I decided to go back to the beginning, and just connect a resistor between two pins of my Arduino module. Sure enough, that also fails DRC with the same error message. Since I’m a new user I can’t attach anything, but here is the content of the failing PCB file:

========

(kicad_pcb (version 20171130) (host pcbnew “(5.1.5-0-10_14)”)

(general
(thickness 1.6)
(drawings 20)
(tracks 4)
(zones 0)
(modules 9)
(nets 2)
)

(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user hide)
)

(setup
(last_trace_width 1.5)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 1.5)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory “”))
)

(net 0 “”)
(net 1 GND)

(net_class Default 这是默认网络类。
(clearance 0.2)
(trace_width 1.5)
(via_dia 1.5)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GND)
)

(module Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal (layer F.Cu) (tedit 5AE5139B) (tstamp 5F5DD0F9)
(at 132.08 109.22 90)
(descr “Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, lengthdiameter=6.32.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf”)
(tags “Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm”)
(fp_text reference REF** (at 3.81 -2.37 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal (at 3.81 2.37 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.67 -1.5) (end -1.05 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.67 1.5) (end 8.67 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.5) (end 8.67 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end -1.05 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.08 1.37) (end 7.08 1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 0.54 1.37) (end 7.08 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.54 1.04) (end 0.54 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 7.08 -1.37) (end 7.08 -1.04) (layer F.SilkS) (width 0.12))
(fp_line (start 0.54 -1.37) (end 7.08 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.54 -1.04) (end 0.54 -1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 7.62 0) (end 6.96 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 0.66 0) (layer F.Fab) (width 0.1))
(fp_line (start 6.96 -1.25) (end 0.66 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.96 1.25) (end 6.96 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.66 1.25) (end 6.96 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.66 -1.25) (end 0.66 1.25) (layer F.Fab) (width 0.1))
(pad 2 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

(module “” (layer F.Cu) (tedit 0) (tstamp 0)
(at 168.7244 98.5366)
(fp_text reference “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(fp_text value “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(pad “” thru_hole circle (at 0 0) (size 2.9972 2.9972) (drill 1.778) (layers *.Cu *.Mask)
(net 1 GND))
)

(module “” (layer F.Cu) (tedit 0) (tstamp 0)
(at 168.7244 112.5574)
(fp_text reference “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(fp_text value “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(pad “” thru_hole circle (at 0 0) (size 2.9972 2.9972) (drill 1.778) (layers *.Cu *.Mask)
(net 1 GND))
)

(module “” (layer F.Cu) (tedit 0) (tstamp 0)
(at 139.5144 98.5366)
(fp_text reference “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(fp_text value “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(pad “” thru_hole circle (at 0 0) (size 2.9972 2.9972) (drill 1.778) (layers *.Cu *.Mask)
(net 1 GND))
)

(module “” (layer F.Cu) (tedit 0) (tstamp 0)
(at 139.5144 112.5574)
(fp_text reference “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(fp_text value “” (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.15)))
)
(pad “” thru_hole circle (at 0 0) (size 2.9972 2.9972) (drill 1.778) (layers *.Cu *.Mask)
(net 1 GND))
)

(module HDR1X18_1 (layer B.Cu) (tedit 0) (tstamp 0)
(at 126.154 93.99 180)
(attr smd)
(fp_text reference JP2 (at -43.9166 2.3876 unlocked) (layer B.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)) (justify mirror))
)
(fp_text value “Header 18” (at -22.0726 0.0762 unlocked) (layer B.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)) (justify mirror))
)
(fp_line (start 1.27 -1.27) (end -0.635 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start -44.45 1.27) (end -44.45 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start 1.27 1.27) (end -44.45 1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start -0.635 -1.27) (end -44.45 -1.27) (layer B.SilkS) (width 0.1778))
(pad 1 thru_hole rect (at 0 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -2.54 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -5.08 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -7.62 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -10.16 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -12.7 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at -15.24 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -17.78 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -20.32 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at -22.86 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at -25.4 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at -27.94 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at -30.48 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at -33.02 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at -35.56 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at -38.1 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at -40.64 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at -43.18 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
)

(module HDR1X18_1 (layer B.Cu) (tedit 0) (tstamp 0)
(at 126.154 116.85 180)
(attr smd)
(fp_text reference JP3 (at -0.7112 45.5422 unlocked) (layer B.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)) (justify mirror))
)
(fp_text value “Header 18” (at -22.0726 0.0762 unlocked) (layer B.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)) (justify mirror))
)
(fp_line (start 1.27 -1.27) (end -0.635 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start -44.45 1.27) (end -44.45 -1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start 1.27 1.27) (end -44.45 1.27) (layer B.SilkS) (width 0.1778))
(fp_line (start -0.635 -1.27) (end -44.45 -1.27) (layer B.SilkS) (width 0.1778))
(pad 1 thru_hole rect (at 0 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -2.54 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -5.08 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -7.62 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -10.16 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -12.7 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at -15.24 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -17.78 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -20.32 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at -22.86 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at -25.4 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at -27.94 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at -30.48 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at -33.02 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at -35.56 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at -38.1 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at -40.64 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at -43.18 0 180) (size 1.4986 1.4986) (drill 0.889) (layers *.Cu *.Mask))
)

(module TACK_SWITCH_3x4x2_no_hole_1 (layer F.Cu) (tedit 0) (tstamp 0)
(at 129.329 113.675)
(attr smd)
(fp_text reference S1 (at -1.6002 -1.1176 unlocked) (layer F.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)))
)
(fp_text value RESET (at -3.4036 -0.5842 unlocked) (layer F.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)))
)
(fp_line (start -5.1816 0.9906) (end -5.1816 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -5.1816 -2.0066) (end -1.1684 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -1.1684 0.9906) (end -1.1684 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -5.1816 0.9906) (end -1.1684 0.9906) (layer F.SilkS) (width 0.2032))
(fp_circle (center -3.1496 -0.5334) (end -2.0066 -0.5334) (layer F.SilkS) (width 0.1524))
(pad 1 smd rect (at -5.5626 -0.5334) (size 1.4986 1.4986) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -0.7366 -0.5334) (size 1.4986 1.4986) (layers F.Cu F.Paste F.Mask))
)

(module TACK_SWITCH_3x4x2_no_hole_1 (layer F.Cu) (tedit 0) (tstamp 0)
(at 129.329 98.181)
(attr smd)
(fp_text reference S2 (at -1.6002 -1.1176 unlocked) (layer F.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)))
)
(fp_text value BTN-0 (at -3.4036 -0.5842 unlocked) (layer F.SilkS) hide
(effects (font (size 0.333248 0.35052) (thickness 0.0762)))
)
(fp_line (start -5.1816 0.9906) (end -5.1816 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -5.1816 -2.0066) (end -1.1684 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -1.1684 0.9906) (end -1.1684 -2.0066) (layer F.SilkS) (width 0.2032))
(fp_line (start -5.1816 0.9906) (end -1.1684 0.9906) (layer F.SilkS) (width 0.2032))
(fp_circle (center -3.1496 -0.5334) (end -2.0066 -0.5334) (layer F.SilkS) (width 0.1524))
(pad 1 smd rect (at -5.5626 -0.5334) (size 1.4986 1.4986) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -0.7366 -0.5334) (size 1.4986 1.4986) (layers F.Cu F.Paste F.Mask))
)

(gr_line (start 170.604 118.12) (end 170.604 113.04) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 100.1622) (end 123.995 101.4322) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 94.879) (end 124.884 92.72) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 123.995 109.4332) (end 123.995 101.4322) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 115.961) (end 124.884 118.12) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 124.884 118.12) (end 170.604 118.12) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 115.961) (end 122.725 110.7032) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 100.1622) (end 122.725 94.879) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 122.725 110.7032) (end 123.995 109.4332) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 124.884 92.72) (end 170.604 92.72) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 170.604 97.8) (end 170.604 92.72) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 170.604 97.8) (end 172.89 100.086) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 170.604 113.04) (end 172.89 110.754) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 172.89 110.754) (end 172.89 100.086) (layer Edge.Cuts) (width 0.1524))
(gr_line (start 137.6094 114.7418) (end 170.604 114.7418) (layer F.SilkS) (width 0.254))
(gr_line (start 137.6094 114.7418) (end 137.6094 96.149) (layer F.SilkS) (width 0.254))
(gr_line (start 137.6094 96.149) (end 170.604 96.149) (layer F.SilkS) (width 0.254))
(gr_line (start 170.604 114.7418) (end 170.604 96.149) (layer F.SilkS) (width 0.254))
(gr_line (start 141.3686 114.7418) (end 141.3686 96.149) (layer F.SilkS) (width 0.254))
(gr_line (start 166.8702 114.7418) (end 166.8702 96.149) (layer F.SilkS) (width 0.254))

(segment (start 131.234 100.754) (end 132.08 101.6) (width 1.5) (layer F.Cu) (net 0))
(segment (start 131.234 93.99) (end 131.234 100.754) (width 1.5) (layer F.Cu) (net 0))
(segment (start 132.08 116.004) (end 131.234 116.85) (width 1.5) (layer F.Cu) (net 0))
(segment (start 132.08 109.22) (end 132.08 116.004) (width 1.5) (layer F.Cu) (net 0))

)

=======

Thanks again for your help!

5

DRC is spitting errors because you are connecting things that are not supposed to be connected. In fact the resistor is not supposed to be connected to anything because it has no nets assigned to it’s pads.

This is happening because you plop components on the pcb without putting them in schematic, wiring them up and importing the netlist.

Go through the proper flow and drc will be happy. If you insist on not using the schematic then use nightly version or wait for v6 which will have some support for doing schematic-less boards. Alternatively use WireIt plugin.
But I don’t recommend this route for beginners, use the schematic.

1 Like
6

Thanks @qu1ck, actually the real board does have a proper schematic, but I didn’t create one for the test file. That gives me a good clue what’s going on though. I’ll go back and look at the schematic and see what I’m missing.

7

Zero errors now, thanks for your help @qu1ck and @paulvdh. I guess I assumed the nets would be auto-sorted somehow. Thanks again for pointing that out, and thanks for taking time to respond to such a dumb newbie question. Cheers!

2 Likes
8

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