ESP32 Footprint DRC Warning

Layout Footprints
1

I hereby certify that I am not simply asking someone else to design a footprint for me.

This is an auto-generated message that is in place on the “footprints” section of the KiCad.info forum. If I remove it and ask for a footprint to be designed anyway, I understand that I will be subject to forum members telling me to go design my own footprint or referring me to a 3rd party footprint site.

Hi, I am trying to finish my PCB design with ESP32-WROOM-32E-N8 I chosed the below footprint and I was doing DRC check. I got this footprint warning what could be the problem and what should I do ?

Screenshot 2025-06-30 at 14.21.27
Screenshot 2025-06-30 at 14.21.271130×569 117 KB

Screenshot 2025-06-30 at 14.13.55
Screenshot 2025-06-30 at 14.13.551738×819 239 KB

2

Have you tried comparing the footprint on your PCB with the one in the Library ?

Select the footprint, then . . .
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3

I checked

In summary it says :
Rule Area on F.Cu and B.Cu layers differ.

In Visual I couldnt notice any difference

4

IF you are sure then you can update it from the Library and then there WILL be no differences :wink:

5

What does Rule are means ?

6
7

That’s a bug: Unavoidable DRC warning for footprints with copper layer rule area (#19694) · Issues · KiCad / KiCad Source Code / kicad · GitLab

You can ignore (exclude) the warning.

8

What version of KiCad are you using ?

Can you paste your version info here please, you can get it from KiCad > Help > About KiCad > Copy Version Info
image