Good morning,
By moving all my PCB, I realize that I have a parasite “Via” that I can not manage to remove.
It has no value if I click on it!
An idea?
By testing the Gerber files on the JLCPCB site, despite specifying that there are 4 layers, I am told an error by specifying that the name is not standard on 2 layers (Probably for In1.cu and In2.cu) and the layer “Groove” is not recognized.
What name is needed for these layers and what to do for the “Groove”?
I got three cuts of PCB.
cdt
There is a Selection Filter in the lower right part of the PCB Editor. In that box you can select whether certain classes of items can be selected or not. Via’s are listed separately, but your via can also be a locked item.
As for the layer naming. It often boils down to reading the manufacturers website and then modify your project to conform to the way they want your data to be delivered. There is a standardized way for specifying V-grooving,(In Gerber X3, maybe also in X2) but as far as I know neither KiCad nor JLC supports it. I think JLC wants lines for V-grooving on the Edge.Cuts layer. (Which does not really work well within KiCad).
Hello
Thank’s Paul
It’s work with the lower right part of the PCB Editor. In that box you can select whether certain classes of items can be selected or not.
The via is deleted now
I will see now on JLCPCB site for the layers names and groove
cdt
cdt
JLC has settings for KiCad V6 here:
They also state:
- Do all inner cutouts, unplated slots, V-cut lines show in the GM1 layer correctly?
I do not know what a “GM1” layer is though.
GM1 is “Mechanical 1"
Just a reminder: uploading the files for their viewer is for your own preview only. It of course works automatically and therefore requires certain things. But for the actual order JLPCB is perfectly capable of handling different things, for example the inner layer names given by KiCad.
There’s no standard name for V-groove or even universally recognized standard way to represent it. You can add it to any layer dedicated for that purpose and communicate with them explicitly. (Unless they have added new instructions for this.)
That is not entirely true.
A “Filefunction” for Vcut was added to the Gerber format in 2017. This means that V-cut information could easily be exported unambiguously on it’s own layer. KiCad does not support it, and I’m not sure if there is much support from PCB manufacturers for this.
You’re right, although by “name” I meant the file name (but that’s true for all layers!). I also deliberately said “universally recognized standard way to represent it” because I had a vague memory about what you say about the standard, and added “universally recognized”. On the other hand that’s true for about everything in the gerber standard. 
Your wording is unclear. So you specified in KiCad there are 4 layers, and when you filled out the JLCPCB form you selected 2 layers, is that right? Well the error message is expected, JLCPCB isn’t expecting the In1.cu and the In2.cu files.
JLCPCB wants V-cuts in the Edge Cuts layer. This will upset the KiCad 3D viewer but that’s the side effect.
I also use jlcpcb and have done several boards with v-grooves. The first one I had just identified the v-groove on the silk layer and they did it properly but then told me to put it on the edge cut layer (.gm1 if you use protel names, which you should, imho). Yes, kicad pukes on drc when anything unexpected is on edge cuts, and 3d render is also goofed up. Here is a board I am sending out (hopefully today) where I define the v-groove on gm1 (edge cut) for jlc:
I am also trying out slotted holes for the first time and will see how jlc does with that. They started telling me a long convoluted process to draw them, but I am just going to see how this goes with simple slotted holes (and a note to draw their attention) as the usb-c jack is just for testing on this proto and if they screw it up I don’t care this time around.
I think it best to use protel names for fab houses – it is an old and common de-facto standard. This is my gerber gen:
In the past I have used Protel names with Chinese fabs, but I have found that they handle Gerber names fine. Their software seems to work out which file is which layer. What they cannot handle are the X2 extensions. It’s the old CAM software they are using.
Gerber files have the function of the file embedded in the file.
Below a copy of the header of a Gerber file generated by KiCad, and on the fifth line there is a “FileFunction” variable that in this case is for the copper top layer.
%TF.GenerationSoftware,KiCad,Pcbnew,6.0.5-a6ca702e91~116~ubuntu20.04.1*%
%TF.CreationDate,2022-05-13T12:54:35+02:00*%
%TF.ProjectId,mumar_base_stm32,6d756d61-725f-4626-9173-655f73746d33,rev?%
%TF.SameCoordinates,Original%
%TF.FileFunction,Copper,L1,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 6.0.5-a6ca702e91~116~ubuntu20.04.1) date 2022-05-13 12:54:35*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
But only if X2 is enabled. If X2 is not in effect, those lines become comments. So their software would have to be smart enough to read comments too if that’s their method. It seems to be a combination of heuristics which work most of the time.
It’s one of those situations where being cheap and not keeping up to standards wastes a lot of time for problems that have been solved long ago.
But I guess they don’t care as long as they are wasting other’s people time.
The only time of mine I spend is unticking the X2 box. I know the purists on this forum keep banging on how we should complain about how they are not keeping up with standards. Frankly I don’t give a f***, I get my boards the way I want. The people that should be pestered are the CAM software houses and fabs. The Gerber standards seem to have been developed top-down and features like V-cut layers haven’t gained traction.
As a follow-up: I submitted a board to jlc today – you just upload a zip and it scans all the files, tells you that it is 4-layer, XxX size, etc. After selecting enig, mask color and such, one handy option is to request production approval (I forget exactly how they phrase it) – then they send their massaged gerber files that they will use for production for you to check in gerber viewer and then approve production. This does put your order on hold, but not by much if you watch for their notification email and check/approve right away. They have a similar option if you are getting assembly (which is great to verify chip orientations).
So I found that a new usb-c connector I am trying out (and made a footprint for) was changed in their gerbers to fatten the pads (and leave less clearance between pads, even though my pads had proper clearance and annular-ring). I figure they know what is optimum for their process so no prob, but I did ask them for guidance on tweaking my fp. This is also my first test of slotted holes. I just made standard kicad oval pth slots, though I did point them out with a note on the edge cut layer.
This was my original footprint (0.2mm clearance and 0.15mm ann-ring):
And this is what jlcpcb did to it:
Since they do flying test probe short/open tests for free, I have no problem with them doing this, but I wish they had told me. It should be a quick qc check to scan through their gerbers, but now I need to squint more to see if they changed anything else. I have had this happen with other vendors as well. But I really love jlc – cheaper and faster than pcbway or myro and a tenth of the cost of a excruciatingly-long 4-week turn at advanced circuits here in the US.
Speaking of adding extra stuff on edge cuts for fab (v-score, slots…) which breaks kicad drc and 3d view, is there a way to put the extra stuff on a user layer, and merge edge cuts with that user layer to create the .gm1 gerber?
Here is what jlc says about it:
"Please kindly make sure that the v-cut lines, cut outs, millings and slots are in the same layer with the board outline. If it is not in the same layer with the board outline, it will be missed. So please kindly check it before you place your order.If it is missed due to they are not in the same layer with the board outline, we will not responsible for it.(If the slots are to be plated, it needs to be with the drill holes in the same layer, or it will be missed easily)."
Not very automated but you could move the cuts to the Edge Cuts layer as a last step before generating Gerbers and sending off. Only a few edits, but you have to remember. Maybe it can be made one click process with a plugin, dunno.
Yeah since these notes are outside of board active area, I stick em on silk until final fab gen. But a layer-merge option would be cool. May have other uses to be able to merge arbitrary layers. I use the user-drawing layer for “hidden-silk” which is for things that extend over pcb edge or extra detail I don’t want on the actual silk. I define that right in footprints with front silk and hidden silk layers (both 0.15mm lines).
All of the gerber discussion above makes me appreciate the kicad developers’ attention to detail which makes kicad a production-grade tool. I had a version of eagle many years ago that had a bug in gerber generation where vias dropping into a hatched grid (which was the style at the time with wave-solder boards) would NOT be connected to the plane if they fit perfectly inside a hatch opening. That took a while to find, and you can imagine the gerber squinting needed then.
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