Erroneous connection 4-layer vias to GND plane


#1

I have a 4 layer board where the GND and power plane are the middle two layers. As you can see from the example below I have a track going from the top to the bottom via a via. The bottom track is shown with an X. The two pink arrows are where I have measured that point to GND and there is a short!

When I have checked over the Gerbers I see this, the blue plane is my GND plane and the Green dots are the via. The via goes stright to ground! There is no relief around it …

This happens at random places on the board … What is going on?

The version used is:

`Application: kicad
Version: (2017-07-08 revision f4ecc417a)-makepkg, release build
Libraries: wxWidgets 3.0.2
libcurl/7.54.0 OpenSSL/1.0.2k zlib/1.2.11 libssh2/1.8.0 nghttp2/1.19.0 librtmp/2.3
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW

  • Build Info -
    wxWidgets: 3.0.2 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.63.0
    Curl: 7.54.0
    KiCad - Compiler: GCC 6.3.0 with C++ ABI 1010
    Settings: USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    `

#2

What does DRC say?
Did you refill the copper zone? (press B)


#3

The via on pin 2 of L911 has clearance but the one on pin 3 of U904 does not. It does look like, as @Rene_Poschl suggested, a case of not refilling the zone or running DRC, which does seem odd. I also wonder why you put vias in the middle of your pads, you certainly weren’t tight for space.


#4

The traces are also very thin. They could be wider because there is enough space for it. (At least in the part of the board we can see.)


#5

When you say “measured” I assume you mean with an ohm meter which implies you have the physical board in hand. But surely not as your layout is unfinished. If you actually sent that off to be manufactured then it is of no surprise that you probably did so without running DRC. You have ref-ids that overlap each other, that overlap pads, and in at least one case overlap an entire footprint. There are tracks, such as from pin 2 of L911, that could have used just a little more attention to detail. But in the end I guess it’s your money. :wink:


#6

Ok. So I have “pressed B” and run the DRC and re-built the Gerbers and the problem seems to have been resolved. I am guessing it will be refilling the copper rather than the DRC process that resolved this …?


#7

If I recall correctly, running the DRC automatically re-pours but I would verify that. Always make a habit to run the DRC right before generating Gerbers, then verify the Gerbers before sending them off to Fab.

The cheaper and quick-turn PCB houses may not ever look at your board files. They will just run what you sent and it would come out shorted. That is part of the low overhead that keeps the board cost down. The more commercial oriented fab houses will ask for a net list and double check, and most times will catch this type of error, but don’t assume they will.