ERC with symbol providing multiple ground outputs


I’m wondering what is the correct way to represent say a power supply, whose connector footprint has more than one ground pin or power output pin. Sometimes this is necessary to reduce current limitations.

I get an ERC error because my custom symbol has more than one pin labeled GND as power outputs. This is representing an off-board connector for which I want to use several wires in a ribbon cable to transfer power.

The footprint could I suppose just have duplicate pads of the same pin number, but I’d like to use the standard unmodified IDC footprint and just have a functional symbol to keep consistent my interface definition. Accordingly I have the opposite connector/interface defined for which there is no problem as the multiple ground power inputs don’t conflict.

Edit : I found this link clarifying my problem. It looks to me like there isn’t a real workaround, stacking pins seems like a bad idea for schematic readability, marking the other as passive yields ERC errors if you drive GND from only the passive pin.


One way to do it is by stacking the pins and giving the hidden ones the type passive. This is the way we do it for the official library. More details about that see the library convention or this FAQ article: Electrical type of schematic symbol pins


You could try only having one GND as a power output and all the others as power inputs. Or conversely (depending on if you like seeing the symbol) have all of the GND pins as power inputs and put a PWR_FLAG symbol on the net near this component (to graphically indicate on the schematic the source for the GND net).


I may consider this, but this surely can’t be regarded as a reasonable solution right? I guess at least the editor needs to be updated so that all the pins aren’t changed once they are stacked.



I don’t understand this part of your FAQ; can you clarify?


This is an oddball problem. How would you suggest to fix it better than the suggestions already provided?

For most, it is not initially obvious why the ERC must work this way to make it work with all the variations in parts. Here is a link that I hope helps to explain why KiCad ERC functions in this way.

ErrType(3): Pin connected to some others pins but no pin to drive it:

Eeschema is currently getting some much needed attention in development. However, as a KiCad quirk, stacking pins appear to be a functional solution.

ON EDIT: The L7805b is a work of fiction created as an example for this feature. Any and all graphical items in this post, even those based upon real parts, are entirely fictional. No animals were harmed during this posting, however, it is expected that if another rodent finds the cheese it’s head will be squashed by the Victor model brand of trap that is baited and set.


You mean the “The symbol editor does not like that” part?

Well if you stack pins and open the pin properties dialog of any one of the pins, then the editor will do changes to the full stack. Meaning all pins will have the same electrical type at this point in time. (Which we do not want in some cases. examples are output pins and power input pins)

At least this was the behavior of kicad 4. Not sure if version 5 still behaves this way.


When I was testing this feature last night, the editor asked for disambiguation since they were stacked. I was able to edit each pin individually, with version 5.0.0 on Windoze.

You might want to update the FAQ.


To me it’s not reasonable because it relies on using hidden pins, and has all sorts of associated bugs. It does work functionally very well.

I don’t think it’s that oddball problem, there are plenty of applications that use multiple pins to source or sink higher current applications where the pins are internally or externally connected.

I’m okay with pin stacking but I think it’d be better if a symbol pin could be mapped to multiple mechanical pins and more readily visible. It could be as simple as just typing 1,2,3,4 in pin number when creating the symbol. The symbol pin could have a visual to indicate that it’s connected to multiple footprint pins so that no information is missing/hidden.


I agree. I really don’t like hiding any pins, even NC pins. I want to see every pin that is on a part in the schematic so when I’m probing around trying to troubleshoot an issue I know what to expect when I touch a pin. Hiding a bunch of power pins by stacking removes flexibility when troubleshooting. If there is a part with 4 GND pins (lets say 3,7,42, and 72, yes it’s a big chip) and the schematic only shows pin 3 as GND and the others are stacked hidden pins. Now the layout has a tall inductor near pin 3 making it inconvenient to connect a probe to. If the schematic showed me that pin 42 is also ground I could easily grab that pin since it is physically in the clear instead of having to find a different component that has a ground connection that is in reach of my probe (short little GND wire on my scope probe).

I may be in the minority, but I feel the value of having all the information right there is worth a little bit of clutter of more pins showing on my schematic. Others are diametrically opposed to my opinion, but I’d still buy them a beer if we met in a bar. :wink: