ERC warning: pin type conflicts when tying unused input pins high or low

Hi folks,

This post is about handling ERC warnings when tying unused inputs high or low - specifically whether unused inputs may warrant their own pin type. Hopefully the lead-in to this question will also serve as a good reference for newer folks just stumbling onto the issue.

Below is an ERC output for a board I’m working on. The warnings are coming from IC’s with bidirectional digital pins which the datasheet says to tie low or high if unused (I tied them low).

For the purpose of producing a working board, these warnings can be ignored. They don’t represent true problems and the board will function just fine despite them. They occur simply because Kicad has been instructed - by way of its Pin Conflict Map - to generate a warning if pins of type “Bidirectional” are connected to pins of type “Power Output” (see below).

I’ve read several good posts from the forum on this topic. The advice for dealing with these warnings generally falls into one of following approaches:

1. Turn off individual ERC warnings. Right click on a warning and select ‘Exclude this violation’. Presumably you will do this for each warning, and only after you’ve given thought to it & decided it’s not a problem. This is a safe, methodical approach, but it requires you to keep a list of exclusions - which for some may get long. Also, to my knowledge there’s no rationale field for exclusions, so it’s up to you to remember why any given exclusion has been OK’d. So a long list is even more problematic. I try to keep my exclusions list as short as possible.

2. Tell the Pin Conflicts map to allow these specific conflicts. Go to File → Schematic setup → Electrical rules → Pin Conflicts Map. Click on the appropriate connection & change it to a green box. Beware: you are basically declaring that a situation which formerly generated a warning will now be allowed. You run the risk of missing true problems.

3. Turn off pin-conflict checks altogether. This can be accomplished a couple of ways. One is to go to File → Schematic setup →Electrical rules → Violation severity. Then change “Conflict problem between pins” to “Ignore”. A second way is to right click on one of the individual warnings in the ERC pop-up & select “Ignore all ‘Conflict problem between pins’ violations”. In either case, it changes the state of pin-conflict checking to ‘ignore’ (see screenshot below), and it will now show up in your ERC window’s ‘Ignored Tests’ tab.

If you use either of these two approaches, the warnings will go away but you once again risk missing true problems - this time because the check is no longer performed. Thus, use this approach at your own risk.

4. Stop running all ERC checks. Yeah, you could do this, but the fact that you’re reading this post says you already see value in running ERC checks because they do catch valid problems. So not really an option. :slightly_smiling_face:

5. Change the schematic-level symbol so the pin types are “correct”. To explain this I need to digress for a moment. Realize that each symbol you see on a schematic has two versions: the library version and the version specific to that particular schematic. The two versions don’t have to be the same - nor do you always want them to be. Often you’ll place the library version of a symbol (i.e. the “master copy”) on the schematic and then tweak it for a particular project - without changing the library version.

OK, back to the main topic: ERC warnings. Yet another solution is to change the pin types on the schematic version of your symbol so that they stop generating warnings. To do this, right click on the schematic symbol → Properties → Edit symbol (do not select “Edit Library Symbol” or you’ll be editing the library version). Change the pin type of each problematic pin so that it no longer generates warnings. You do this by right clicking on the pin in the symbol editor → Properties, and then using the drop-down to change the pin’s electrical type. These changes only affect the symbol in that particular schematic. The library symbol is unchanged. (The downside is that you’ll still get a warning for each symbol whose pin types were changed because the library symbol no longer matches the schematic symbol. But it probably results in fewer overall warnings.)

In my case, I have pins of type “bidirectional” connected to pins of type “power output” and I’m getting ERC warnings. if I changed my unused pins from “bidirectional” to “passive”, they would stop generating warnings because the Pin Conflict Map shows a green box where “passive” and “power output” connect.

6. Create a library-version symbol for every different possibility. In theory you could create several library versions of a symbol - each with different unused pins. Then you could load whichever one was appropriate for the project. But this seems like a crazy amount of bookkeeping. I mention it here only because it IS possible.

So, I’m planning to use approach #5. There’s a minor problem, however: if I ever decide to use one of my unused pins, I have to remember to change the pin type. It’s declared “passive” and will give almost no warnings. That’s because the Pin Conflict Map shows that a passive pin can be connected to almost anything & still get a green light.

This made me wonder whether a new pin type would be useful. It could be called “Unused” or something similar. It would generate no warnings when tied to a power output, but the moment you tied it to anything else (e.g. an input, output, bidirectional, etc.), it would give a warning. This would force the designer to change the pin type if they ever decided to use that pin. Plus it would be a very intentional way of handling what I’m guessing is a common problem.

That said, wish lists are always long and I certainly don’t think this is a critical need. Many thanks to the Kicad developers for accomplishing what they’ve already done - it’s a great tool!

Curious to know what others think - and thanks!


I’m sure you have your reasons for connecting power nets directly to signal I/O, though it’s not a very nice approach and bad design practice.
But your solutions seem overly complicated. Just place a 0-ohm resistor directly on the pin in question, or create a “pseudo-VDD” net from VDD through a 0-ohm resistor.
Problem solved.

Even if configured as inputs, in the startup phase MCU pins may act as outputs (mostly low) and draw huge amounts of current or even latch up.

KiCad is quite simple and straight forward.
If a pin is defined as bidirectional, then you tell KiCad that it could be either an input or an output, and connecting an output to a power supply rails is an ERC violation. KiCad does not know whether your bidirectional pin is an input or an ouput at that time. And ERC is right. If there is any chance in your design that a pin may (even temporarily) become an output, you should never connect it directly to a power rail.

A safe option is to insert pullup or pull down resistors, they are cheap, but take up PCB area, and placing them costs more then the things themselves (although still cents).

A simple solution is to just set these pins to “passive”. In that case ERC allows all connections, and you have effectively disabled ERC for those pins.

And intermediate solution is to add Net Ties on the schematic (and on the PCB). On the PCB’s these are just pieces of copper, so they do not add manufacturing costs. You do need a bit of room to put them on the PCB, but you can define a net tie with the same with as your tracks, so the final result will be invisible.

I am reading and I am using this solution :slight_smile:
I was using Protel for years. Important is what way I started to do it. PCBs were designed by someone else until we made a decision that I take this from now on. I was taught step by step how to do PCB and ERC was not in those steps. I have never time to read Protel instruction and no time to check what there are in menu except what I am using. So I simply never found ERC. I didn’t searched for it as simply I didn’t needed it. I have heard about ERC for the first time when I started reading this forum (2017).

GND is also power net.
To better protect unused I/O pins against nearby ESD I see nothing wrong in grounding them all. Why it is a bad design practice?

Adding element to cheat ERC seems for me being pointless.

And distribute that net paralelly to VDD?

Never heard about it. I was sure that for all MCUs during reset all their pins are HiZ and will not be an output if program will not set them to be output.

Many people read “…tie unused pins to GND…” and skip the “…via a resistor…” part.

What I said is not about if or how they should/can be connected to GND but if really

I was sure that during reset all GPIO are HiZ.
Or may be you are speaking about what is happening before reset - when voltage is low enough to not correctly propagate reset state to all parts that they should be correctly set by reset?

It is what I read (not even remembering where) and I am not expert enough to elaborate further.

Because it’s not an input, it’s a “bidirectional”, meaning potentially an output. Of course ERC should flag that, otherwise it’s not doing its job. And you never know how good your FW is. Use a pull-up or pull-down, THEN it’s good design practice.


A bidirectional pin can act usually either as high-impedance input, output low, or output high depending on the initialization phase and what you do in software. Connecting a high output to GND creates a short circuit and will likely damage something. So it’s usually much better practice to connect unused pins with e.g. a 10k resistor to GND as it’s grounding the pin, but also limiting the current in case the pin is set to an high output for some reason.

Long time ago (previous century) we (by chance) noticed that our device can be reset by cellphone calling in the close proximity to it (around 10cm).
We decided to try to find the way to protect our device against it (you can assume it as over-engineering, but we always try to do everything the best we can). The effect of such approach was that when we (Poland) joined EU in 2004 and CE and EMC started to be mandatory when I went with our devices to EMC lab they told me that I was their first customer who passed all test for the first time. As EMC was not a subject before and suddenly all had to do tests they told me that typically people come to them with the same device 2…5 times.
The reason those time was a short track connected to reset pin and left open (it was used to program MCU only and MCU had internal pull-up). 10k resistor practically not helped. 1nF helped. My conclusion was that if reset pin can receive such noise than each input pin can receive. Pulses are probably too short to be read by program, but if you set slope interrupt from pin …

I left all unused MCU pins open and set them in software to be output 0 (in my opinion better than input with 10k outside with even 1cm track acting as antenna). But there was one device that I shorted directly to GND all MCU pins except 2 used to connect USB. It was pendrive like device covered by 2 part plastic box so ESD could easily jump inside and that devise passed EMC tests.


Love it when a thread turns to “anecdotes”. Then it’s time to quit. Ciao.

With modern MCUs you often have a choice of internal pull-up or pull-down on GPIO pins. So you could just initialise to one of those and leave the pin NC, avoiding all this tying to GND or VCC.

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