I like to use ERC to find root causes of errors and bugs. But ERC errors are
false as shown in the attached schematic.
Check what the pin type on the battery symbols is - you probably need to change them to Power Output, or add a power flag to the nets.
I don’t use ERC ever but here it looks ERC is correct.
If V1 and V2 had pins defined as power output than you will be not allowed to connect them together (connection between V1 and V2) as you would get two power output pins connected together. So I believe their pins are not defined as power output.
So you have 0 power output pins at your schematic and you have 3 nets containing power input pins.
I just assume that V+ and V- pins are defined as power input (power symbols (GND in this case) are defined as having power input pins (this allows to connect many of them together).
From what I can see, KiCad is correct here. For more background info you can look up the usage of the PWR_FLAG symbol. Some people think this check causes more trouble then it’s worth, and dislike (or misunderstand the PWR_FLAG symbols. If you think so too, you can disable this check. I’m not sure if other EDA suites even attempt to check / verify this.
Battery symbols? These are not batteries, but spice voltage sources. (But you probably can assign battery footprints to them).
The pins of voltage sources and batteries and such can not be defined as power outputs, because these things can be used in series, and if they were defined as power outputs that would connect multiple of them together, which is illegal in ERC terms. And the same for power and GND symbols.
Simulation sources are not “power outputs”. You need to add PWR_FLAG to the three nets.
ERC is completely correct.
Battery, SPICE source, whatever. It’s just a symbol.
That’s incorrect - there is legacy behaviour that will connect all hidden power input pins on a symbol together, and all power symbols of the same name will be connected together as a global net (see documentation here: Schematic Editor | 9.0 | English | Documentation | KiCad).
Editing a non-power schematic symbol to change visible pin types will not change the connectivity.
Connecting power inputs together is indeed perfectly normal, but connecting power Outputs is not. See: Schematic Editor / File / Schematic Setup / Electrical Rules / Pin Conflicts Map.
S4.3 Rules for pin stacking - Library Conventions | KiCad EDA also explicitly mentions:
- Connecting
OutputorPower Outputpins would result in an ERC error. Output pins that always need to be connected together must therefore be stacked. The invisible pins get the pin typepassivein this case.
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The power flag is not required to run a simulation. It is a feature of ERC which knows very little about simulation symbols.
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The power flag was needed in the past when the same symbol was used for power and signals. The symbols have changed, the power flag is redundant, but ERC has a few flaws.
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The KiCad Simulation Demos are for a mixture of past KiCad releases. They need to be updated to match the latest release. Please run ERC for every simulation.
Sorry, but JamesJ is correct. I just tried it out:
Two VDC sources in series, where the pins are changed from “Passive” to “Power output” do not cause ERC errors. Try it.
But it’s an illogical exception that might need to be pruned. I’ll leave that to the developers.
Ah I see what you mean - I wasn’t meaning (nor was I clear) to set them all to Power Out, as the series ones will inded give an error. You just need one on the net set to power output (or, as above, just use a PWR_FLAG, which is the simplest approach).
In 9.0.2, this does correctly result in an ERC error with the default pin conflicts map. I had misinterpreted what Paul was saying above.