Unlike with PcbNew, I make little use of ERC on schematic because it generates so many false positives due to pin types.
I have just been bitten with an accidentally islanded net and think that having a hierarchical label on a sheet without a corresponding sheet pin one level up should be detected as a more serious error, maybe generating a warning at the create netlist stage
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Done
What is nasty about this is that you end up with two nets:
“netnameXYZ” and “sheetABC/netnameXYZ”
Both are displayed in PcbNew as “netnameXYZ”
You only see the difference by inspecting the netlist with a text editor