ERC ErrType 5 Issue

Hi, I am new to Kicad. I have a simple schematic where I want to create a PCB to bring out the pins of a component to a 16-pin header. I am getting Type 5 Errors from the ERC. I checked the pin Electrical Type and they seem to be correct as far as input/output. However, it seems as though the ground symbols are on the same net and, therefore, make the output pins connect.

The rule is simple, you can only have one output or power output on the same net.

The RF_GND pins on U1 should probably be power input, not output.

The GND pins on J1 should be power input, not power output.

@bobc gave you the answer for this particular problem. It might be a good idea to read this FAQ article: Electrical type of schematic symbol pins (KiCad 4 and KiCad 5)

Thanks for the reply. Here is the updated schematic.

I disconnected pins 8 and 9 on U1 from ground and connected them to J1. They are actually the Return for the VDC on pins 6 and 7 so I connected them to J1 to enable the two twisted pairs with VDC and Return on the header pins. On pins 15 and 16 of J1, I did as you recommended and changed them to Power Input and now there are no ERC errors.

I do have a question, though. I thought that a Power Input pin and a Power Output pin had to be connected together. By changing pins 15 and 16 to Power Input, they are both connected to Ground Symbols which have Power Input electrical types. Why is this not an issue?

Thank you very much!

Thank you for the helpful tips!

Unless U1 has hidden pins, there is no connection to VCC and U1.

Each power net must (for ERC sake) have one (and only one) output, but can have many power inputs/passives/etc on it. The power symbols are just global connections with commonly used and recognizable symbols. This is why power flags are sometimes necessary. If your power source is (for example) a header commonly the pin type would be passive. Or another example is if your power source goes through a polarity protection diode (or mosfet). In both these cases there wouldn’t normally be a power output pin on the net. But, if the power source is a voltage regulator then there would be a power output pin on the net and the power flag would be unnecessary. (I haven’t played around to see if it would throw an ERC error if there is a power flag on a net that has a power output pin.)

Something that would be nice (eventually) for ground fills, is somehow communicate the “source” of the net (if there is a power output pin, or by requester if there isn’t a power output pin) when making a net-connected flood fill in pcbnew. Then the fill algorithm would pour from that point, and only that point. Then isolated islands wouldn’t be filled until the designer manually stitches to into where the island would be. I may make this suggestion once v5 is stable as a request for v6.

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