I receive a warning which indicates that a net has two names. I don’t understand why KiCad figures that this is two names for the same net. What I have done is used two pins for the signal and connect them together on the pcb, but KiCad ERC insists that they are for the same net. I would think that they are two nets with different global names that are connected together on the pcb. Is there no way to make two wires carry one signal?
How about a Dot-OR is that also impossible?
In fact I also use three separate pins for switch signals that require identical processing so on the board they can be Dot-OR’d together to be processed as one, but they are distinctly separate in origin, coming from different places on the machinery. KiCad is not bothered by that. The names are different, but so are the global labels for these pins mentioned first.
Am I missing something?
Can you posr the schematic or a image of it?
I guess not. I decided to change the schematic by deleting the one pin and tie them together by placing a trace on the pcb. That is how I did the Dot-OR, I believe. What I did was use Global Labels for all of the pins of a connector and five of them used two pins or were not used. I deleted the duplicate pins and then get the not used elsewhere error.
I was going to try to take it from a backup, but the last backup had too many errors that I had already fixed so it would confuse the issue.
The pins are on a connector: two of them are inputs and three are outputs. The outputs are outputs from a ULN2003A Darlington so each runs a relay. These outputs have nothing between their driver and the connector (the relays are at the end of a cable a couple of feet away.
The inputs are the motor controller’s direction switch; one runs forward and the other reverse. They are inputs to the microprocessor through a voltage divider to lower their voltage. The processor uses them to determine the direction being signaled to the motors.
My question has to do with how one approaches using two pins for one signal and also for Dot-OR situations. KiCad seems to prevent that from happening. It is only a warning so I told it to ignore them, but it is kind of a pita to have to mess around with it. The ERC is unrelenting. I guess that is somewhat its intended use - to make sure all things are addressed.
If two pins are carrying the same signal, they are (pretty much by definition) on the same net. So, just put them on the same net. What is your thinking that they should be on different nets?
(BTW, there is a way to join nets, using a “net-tie,” but that seems to me to be asking for trouble).
I want to distribute the current between two wires rather than one due to the relatively high current and the distance to be driven down the cable. That is technically not the same signal, rather part a and part b of the same source signal - each is different due to the characteristics of the wires, though very similar. The reason they are different is that they are named for the pins that the signals come to the board on and carries that knowledge and that is how I should be able to represent them. That makes them two nets and allows me to put them together.
I really don’t see why it be somehow automatic that two or more wires Dot-OR’d together are a single net even if they are not identical. That seems rather arbitrary and limiting - needlessly.
What is Dot-OR? I don’t find anything by googling.
As far as I know, every EDA software works this way. The schematic defines nets, all items in a net are connected together and must be connected on the PCB. If you need a direct connection on the PCB but want more than one net, you use something like a net tie which connects two nets electrically. In KiCad a net tie is “component”, a symbol and a footprint.
That’s the definition of a net in KiCad. But you can achieve your goal of more than one trace between two points by allowing duplicate traces in the settings.
If a digital signal on two or more conductors are tied together, the resulting signal is a logical OR of the original signals.- it is called a Dot-OR because there is no physical gate and the single wire will have an ‘up’ on it when one of the wires is ‘up’ and a ‘down’ when all of them are ‘down’.
I have no problem with KiCad not supporting that directly, as long as I can do so without an error in some manner which keeps it from happening. I was misunderstanding how ERC works because it was preventing this from happening and also preventing me from getting past it. Of course, ERC is only warning and I can allow it to ignore the error if I want.
My only desire was to find out if KiCad will allow the Dot-Or, that is, the functionality of it. And it does.
Dot-ors e.g. for an I2C bus, can pass ERC. Pins can be joined and pass ERC, e.g. using a NAND as an inverter. It’s probably just the way you expect to label your pins.
I do not want more than one trace between two points on a pcb - my wish is to have two pins with the same signal source on both that are connected together on the pcb that I can reference according to the pin the signal arrives on. That pin number would be the name of the signal on the board. This should be consider as two nets that are Dot-OR’d together and the output of the Dot-OR treated as another net. It should not require any limitation to a net - it needs to be capable of identifying the point at which the Dot-OR’ed signal occurs and its multiple components should bear different names. I have done this on KiCad, but it makes it very difficult due to my misunderstanding of ERC.
It is not, period. Find some other way to label to notate the way you want.
I am only slightly familiar with I2C, but my impression is that it is a serial port with data on one line and a couple of control lines - not a Dot-OR. But I don’t know.
As for using it, I have produced a design in KiCad that uses Dot-ORs as I described previously and I did it by having the ERC objections ignored - but it did object.
OK I was hoping someone would tell me how to do it and I know how now. Thanks.
The I2C lines are open collector (or should that be drain these days?) drive with a pull up resistor so any bus member can pull it down. So it’s a dot-or in inverse logic where low = true. Same concept.
I still haven’t completely understood what is what you need, but it sound like net-ties, maybe take a look if the help you with what you want.
KiCad has symbols and footprints for them, just could not find the documentation 
Yes I think that net-ties are what I need to use. I have done two pcb designs without them in KiCad but I think I’ll change them to see how it does. KiCad has been one bundle of frustration for me!
I also noted the same problem with voltage - I have two 5 vdc regulators taking power from the 12 vdc battery. One of them operates proximity switches which have three wires open collectors and negative ON characteristics. I provide pullup resistors on the input and power/gnd for each switch from the pcb. There are as many as ten switches each with its own four-wire cable. These cables connect through a connector to the pcb. Of course I connect all of the pins together, but KiCad does not like that - if it treated each one as a separate net it would work. But there seems to be inconsistency between how it treats power pins and the other items on the board. If I connect each of the pins involved to the +5V, it works, but if I connect one +5V power flag onto the group which are all tied together with copper, it flags it as an error.
So I know something isn’t right, but I also know that I can do this normally. It seemed to me that identifying a net as essentially one wire or trace would solve the problem, but it apparently confuses the issue in other situations. That is why I am looking for a different solution. Net-ties might be it.
Another thing - I repeat though: two wires connected to the same source do not necessarily carry the same signal to the other end and I think that KiCad doesn’t allow for the difference that the wire causes.
One more thing, if you draw two separate nets without net-ties to the same point as inputs and then identify the output net as a different net, KiCad objects. Which is good and then you can tell it to ignore the ‘error’. This is effectively a level two net-tie, but I am using KiCad 6 and heard nothing about net-tie until now. So this might be what I need.
KiCad, and every other EDA tool I’ve ever seen, treats a net as a group of connected pins. Not a wire or trace. You can’t have two different traces that both connect the same pins and call them different nets. There are various reasons why this is the case, but I won’t get in to them here. I just wanted to say that the tool you are looking for to deal with this situation is definitely a “net tie”, as others have pointed out.
It is wrong to think of a net as the set of wires in a physical implementation that all have the same logic state. A net is a set of pins that must be physically connected together on the PCB in the PCB design software. There may be many nets that share the same physical/logic state at the end of the day. But when you describe net connections in the schematic editor, you are not describing the set of things that function together electrically – you are describing the set of things that are physically connected together by shorting copper on the PCB. You can see there is a subtle difference between these two concepts.
Perhaps the “inconsistency” you mean is that KiCad does specific ERC checks for power pins that it does not apply to non-power pins. Once you understand the (fairly simple) logic behind KiCad’s ERC, you can understand what scenarios it checks for and what types of errors it will catch (and importantly, what types of errors it cannot catch for you).
It is useful to view electrical pin types not as “what is the most accurate description of this pin” but instead as “what is the role I want this pin to play in the ERC”. The power pin ERC is checking that every net with power input pins has one, and only one, net with a power output pin. This helps to prevent accidentally leaving some parts unpowered, and accidentally connecting the output of two power supplies together so they fight each other.
As you may be thinking, there are many scenarios where you might want to connect multiple “power supply outputs” together, or when you don’t have a power supply on your board and therefore there won’t be any power output pin! KiCad’s ERC is not capable of understanding the art of electronics – it is just following simple rules. So in order to reason with it, and get rid of ERC errors, you just have to think about what it is actually checking for, and it will usually become clear what you need to do to get rid of false-positive errors while still leaving the checker turned on (so it can catch real errors)
Thanks - I think I understand your points. Re: “every other EDA tool …” I agree that in almost every case the tools apply the same kind of thinking regarding nets. The suggestion I was making had to do with allowing deviation from the obvious rule. And guess what - that is exactly what KiCad has done for power pins. What I was asking for was a way to designate the nets. If pins 4, 5 7 and 9 are connected together and designated as net 4-9 while pins 2, 3, 6 and 8 are connected together and designated as net 2-8, then designate a final net comprised of the two nets in a single name such as net 2-9 for example. It sounds like a net-tie could be used to merge the two nets. That by itself and in conjunction with how power and grounds are handled shows quite definitively that the problem has been addressed at least in part previously (separated grounds and separated power sources). I am merely pointing out that the general concept for nets needs some rethinking because it does not provide the same kind of flexibility for non-power nets.
In my case, I have several relays that are operated off-pcb through pins on a ribbon cable. The ribbon cables have fairly small wire sizes, so in the design, I used two wires to carry the signal that controls the actuation of each relay so I need the same kind of capability as the net-tie fools KiCad with or that the power flags Gnd and Vcc are blessed with so that a regular net could be created in a similar manner. I suppose that technically I could identify that the open collector IC involved is a switch and a ground. (Hmmm KiCad has a different way of handling open collectors, doesn’t it. I should look into that. KiCad might already have what I need (not net-tie). I’ll have to look for that, too.)
Anyway, the ribbon cable connections for electronic signals uses every other pin as a ground which are all wired together on the pcb to provide noise reduction over the cable. But the power pins are each two wires. Each of the voltage pins connects directly to one of the proximity switches and each signal pin has a ground wire shield plus the return ground line from the switch. KiCad allows me to hook all of the grounds together, but complains that the +5V lines are connected together. I have to put a +5V power flag on each pin or tell it to ignore the error. But this same methodology is not allowed on the 2-wire nets. I think what I am missing is to make my own power flag for these relay ground pins.
Hope this adds some additional clarity as to what I am looking for.
I’m not trying to be rude here, but I think you still don’t quite have it. There is no difference between the handling of power and non-power nets except for a few ERC checks.
There is no concept of “final net”. A net tie just specifies that two different nets are to be connected together at a certain point on the PCB. They still remain two separate nets.
I think it would be helpful for you to show a screenshot of what you are doing today. Something sounds off to me.
I don’t care if KiCad says they are one net, but it prevents me from passing the ERC and I can’t get the board made. If it allowed me to designate the name of the net and distinguish between the two half nets, then combine them into a third named net, I think I would be happy. But I could not find a way to do that so I asked here. First time I have run across the concept of net-tie which appears to be a way to fake KiCad out.
Why do I think they should be on different nets? In my case, I have several relays that are operated off-pcb through pins on a ribbon cable. The ribbon cables have fairly small wire sizes, so in the design, I used two wires to carry the signal that controls the actuation of each relay so I need the same kind of capability as the net-tie fools KiCad with or that the power flags Gnd and Vcc are blessed with so that a regular net could be created in a similar manner. I suppose that technically I could identify that the open collector IC involved is a switch and a ground in a custom symbol similar to a net-tie and KiCad would no longer flag it.
Anyway, the ribbon cable connections for electronic signals uses every other pin as a ground which are all wired together on the pcb to provide noise reduction over the cable with no complaint from ERC. It will even allow a ground plane. But the power pins are each two wires. Each of the voltage pins connects directly to one of the proximity switches and each signal pin has a ground wire shield plus the return ground line from the switch. KiCad allows me to hook all of the grounds together, but complains that the +5V lines are connected together. I have to put a +5V power flag on each pin or tell it to ignore the error.
If I was allowed to name the nets and if the names are different, KiCad should allow me to merge two nets with different names into a third net with a different name, allowing me to decide what the net is. However, I assume that the definition of the nets is set in concrete and that forces the requirement for deceiving KiCad with net-ties and special forms of nets such as grounds and various power flags to give the ability for doing what I need for grounds and power sources without allowing a similar functionality for run-of-the-mill nets…
All that said, it seems that this same methodology is not allowed on the 2-wire nets. I think what I am missing is to make my own power flag for these relay ground pins which no one has suggested that I do.
Hope this adds some additional clarity as to what I am thinking.