ERC error when connecting Inputs to Outputs via a Bus

KiCAD: 7.0.10

If i wire an “Output” pin from a hierarchical sheet to a symbol with an “Input” pin, I do not get any ERC errors.

However if I take that same net and put it into a Bus, then unfold a wire from that bus, then wire it to the “Input” pin I get an ERC error about the pin not being driven by any Outpu pins.

Is there something I am missing?


I think you need a CS1 label on the CS1 output wire from the Microcontroller. The bus doesn’t automatically label the wires connected to it.

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Hey thanks for the reply.

I confirm that putting a CS1 label on the bus input side wire fixes it.

But this somehow not satisfying:

  1. If the bus input wire from the microcontroller was not already known to be CS1, then I would get a warning that the wire is connected to a bus that it is not a member of. So KiCad does knows CS1 is a bus member without adding an input label.**

  2. If you always have to manually label the wires on both sides of the bus, the utility of a Bus isn’t clear. In all cases then (except where a bus passes into a hierarchical sheet) you could delete the bus and have exactly the same schematic get the same result. Are buses supposed to be a purely cosmetic guide to the eye? I suppose so! Labels on both sides appear to be how its done in all the documentation.

I thought avoiding excessive labels was a key function of a Bus, in that a label allow for mysterious behind-the-scenes connections to unconnected parts of the schematic. But I guess this is wrong?

** Actually, something odd is that in 7.0.4, if you connected a wire from a hierarchical sheet then the Bus needed to be labeled with {SheetName/Label}, in my case Microcontroller/CS[1..8] but in 7.0.10 this naming convention appears to have changed. Now you use {CS[1…8]} to avoid the warning.

KiCad has no way of knowing that you intended to connect CS1 of U2 to CS1 of Microcontroller. You may say, but I labelled the pins CS1-8. But you may actually wish to connect them in a different order. And maybe you didn’t label the Microcontroller pins CS1-8 but OP1-8. Maybe it could suggest a “guess” but you still have to give it the correct instructions.

A bus is still a connection by label method. What the bus can do is enhance error detection, by not allowing you to use a net that’s not a member of the bus. You can also autoincrement when connecting lots of members.

Sorry, I don’t understand your reply.

I understand the need to label outputs.

My pint was about input labeling. It already knows there is an input wire CS1, and that wire is going into the bus. Therefore, I shouldn’t have to label the input wire. It does not lift any ambiguity I can see.

How does the Microcontroller end know which of the bus members should be connected to the CS1 pin? Or alternatively how the U2 end know which bus member is connected to that pin? You have to label both sides. It’s symmetrical.

The input side connection already has an implicit label, that why I don’t get a warning on the bus input connection

Where is the implicit label? The hierarchical pin? What if it’s not called CS1?

See below. It has a net name without the input label (bottom left gutter)

This is related to my ** footnote above. The implicit naming scheme changed from 7.0.4 to 7.0.10.

I don’t see a Net Name. I see a Connection Name: /Microcontroller/CS1. I’ll let somebody else delve into the subtleties of hierarchical pins and names, it’s too late in the day for me, but I think it would be a error to have an implicit label because that could result in a wrong connection. What if you really wanted to connect U2 to CS2? Maybe this was a 7.0.4 bug that got fixed.

Wires going into (or coming out of) a hierarchical sheet do not have a name. Any wire connected to a named bus has to have a label to identify it. KiCad does not make assumptions here. You almost certainly have ERC violations for those unnamed wires on the bus. They may be off screen, or you may have disabled them.

When working with buses. it is easy to drag a box around a bunch of labeled wires coming out of a bus, make a copy of the selection, and then use mirror and rotate to get the other side of the bus to connect.

On a higher level, you can also put a named bus directly though a hierarchy. You do not have to separate all the bus members into individual sheet connectors.

I do not have a warning off-screen. See the attached screenshot or simplified project.


TEMP_BusTest.zip (11.5 KB)

In your example you already have 2 instances of “Warning xxx is graphically connected to bus yyy but is not a member of that bus” and another error for your hierarchical sheet wire not connecting to anything.

I appreciate you creating and posting a test project (you don’t have to include the backup directory in such an upload) but in it’s current state your test project is both too simple, and too complicated.

At the moment I am wondering why you do not get an ERC error for the first example. Maybe there is some interaction between the other parts of the schematic. I have modified your test project a bit to experiment with it more. I added some resistors so at least KiCad has some attachment points to connect things to, and I added and changed some names. I’m not entirely sure what is happening here, but it looks like you stumbled into a bug. It appears that an auto generated net name is (half) accepted as a bus member, while in my opinion this should never be accepted as a valid construction. It’s too easy to make errors this way.

2024-01-18_TEMP_BusTest.zip (8.1 KB)

Thanks for taking the time.

Yes, I expect to get errors from the second two; i included them to compare with the first.

The fact that I get an no error for the first one is my point above about the implicit label. That bus is clearly happy, so I thought it was intended behavior.