Hi, Kicad noob warning (but I know electronics design) I use kicad-nightly-r31042.82a1175d72-x86_64.
Two (three) things could improve ERC messages
I miss an electrical type to use on an internal biased pin. A pin that is ok to leave open or connect to driving signals (driven by external outputs, or resistor network). I want it to not give warnings if unconnected, or connected to an ouput, but I want warnings if connected to other inputs only.
When I connect a power output pin only to a power symbol, and nothing else, I want to get a warning saying “power pin not connected” or similar. Todays daily does not pick this up as an issue. I think it should.
Bonus request: I work with several digital voltage level signals on the same design. For input and output pins, I would love to be able to select reference voltage, either as wich power input pin on the symbol is referenced, or - In case of internal voltage regulator - a specified voltage level. This could make KiCad’s ERC pick up logic driven with wrong logic levels. This is VERY useful.
All pins that are not connected to anything generate an ERC warning in KiCad. If you want to leave a pin unconnected on purpose then place a No Connect flag (small blue cross) on it. This is KiCad’s way of it knowing you did not leave it open by mistake.
You may be right here but I think it’s outside the scope of ERC. I made a test project, without the +5V power symbol the output gets flagged as “not connected”, while with the power symbol it is still a 1 pin net. And what if there is an output filter cap on the output? I’m not sure whether this should be flagged by ERC though. Voltage regulators can be used in weird ways (for example as a reference only, there may be a series fuse, etc).
This is far beyond the purpose of ERC. It’s more like spice like than ERC. It would also get complicated very quickly, for example 4000 series logic can be powered from a few volt to 15 volt, and lots of uC’s and other stuff can have supply voltages down to 1V or even lower. It would be nearly impossible for KiCad to keep track of all such things.
I disagree with your conclusions. I think your comments are pure get-aways and not helpful for me as an electronic designer. I have 25+ years experience with this.
Can be done. Will it be useful? Yes i think so.
Disagree strongly. It can be done and it will find problems at schematic level. In other words, its an Electrical Rule Check job.That is why it should be done. ERC is not a graphical rule check, but an electric rule check.
Yes, this is a rather big workload, but its doable AND its a useful ERC job. Corner cases can be discussed. This would be a great feature with great advantage over commercial software.
When it comes to 3, no I have not seen it. That doesn’t mean it won’t be useful I have most experience with Eagle and this is surely a feature I miss. I work with rather large FPGA designs where there are several IO voltage levels in the same design, like 5V(external IO ports), 3.3V (common micro controller IO) ,2.5V (some interface IO), 1.8V (FPGA generic IO) and 1.2V (FPGA/DDR4). Small things like i2c buses and IO expanders often need level shifting, and the ERC have a great potential to make sure this gets done right before the PCB is drawn.
I do not want to go into details how to solve it, but if there is any interest in the community, I will be active in the discussions. I have a few different ways to solve it in my head.
PS:
For Eagle:
can be solved by setting the pin to “hiz”, although this is not catching “hiz” to “input” only connections.
This is a disaster in Eagle. KiCad does better today, like catching two power outputs connected, wich Eagle doesn’t. Eagle doesn’t even check if a power input (pwr) has a power output (sup) connected.
In other words, Eagle functionality is not something to aim for.
Regarding 2), I noticed S7.1 Power flag symbols - Library Conventions | KiCad EDA
This probably explains why it is not triggering a warning/error. The power symbol behaves like a physical device. Power symbols must be treated like a page connector only. I would think this is an easy issue to fix.
I have most experience with Eagle and this is surely a feature I miss. I work with rather large FPGA designs where there are several IO voltage levels in the same design, like 5V(external IO ports), 3.3V (common micro controller IO) ,2.5V (some interface IO), 1.8V (FPGA generic IO) and 1.2V (FPGA/DDR4). Small things like i2c buses and IO expanders often need level shifting, and the ERC have a great potential to make sure this gets done right before the PCB is drawn.