Good morning,
In PCBNEW (Kicad V7xx), I would like to be able to indicate for each component the maximum operating voltage that can appear in operation.
In the case of low voltage circuit design, there is no real insulation problem, on the other hand, in the case of the presence of
high voltage (for example 600VDC), the definition of insulation rule via KiCad netclass causes an inflation of DRC errors, which requires
infinite time to “sort out” what is relevant or not.
For example, if we use only a gate resistor of a type P mosfet (R between source and gate), the terminals of this resistor
and the gate-source insulation of the mosfet P show an insulation error when there will be no more than twenty volts between
source and grid???
Thus, we can simply indicate the maximum operating voltage for a component, a parameter which is perfectly known at the time.
of the design of the diagram? (otherwise, we don’t care, which should not be the case for a professional designer of electronic diagrams)
And it would also be cool, for the nets this time, to indicate the average service current…We could even give a percentage over time
for for these currents.
In this way, the rules for insulation and dimensioning of tracks could be, I think, quite simply constructed automatically by
the layout part (PCBNEW).
Is all this, or would it be possible?
Thank you in advance for your answers.
I use netclass to specify little higher clearance then for the rest of PCB. But my high voltage circuits are 24V
Using simply netclasses you can’t specify clearance between nets belonging to your HV netcalss and the rest of PCB without at the same time that clearance be DRC required inside HV netclass (between nets belonging to HV).
You have to use rules to specify your requirements.
But I have never even tried to use rules and don’t know where to find a good set of examples.
May be others can help.
Yes, that’s what I do: In addition to the “Default”, I have dozens of them.
But the problem is that if certain tracks carry either voltage or current (1), monitoring (2) of the U and I on these tracks (by a µP for example) only requires a very low current and therefore does not necessarily require a track width other than the “default”.
(1) Process similar to “Writing”
(2) Process similar to “A reading”.
So, it’s obviously “the same net”, but “not the same destination”: I don’t understand that all this brain juice that KiCad constitutes is not from the start differentiated the reading and writing processes vis-à-vis with regard to the notion of “net”. However, these 2 processes are the foundation of all communications (and therefore of existence), moreover they are inseparable from each other ("everything that is written but not reread does not really exist in fact for us !): Writing & Reading are “atomic” and KiCad doesn’t give us any way to “break that atom”…
I found a way to get around this essential problem…but it’s a hack: Too bad, too bad.
Thank you for your kind response.
post Scriptum
There is even a PB with the “unconnected” pins of the same component: Not being connected, a pin takes the “default”, and as it is not equipotential, it possibly comes into conflict with pins adjacent of the same component!!!
And in this case, at the level of the diagram, we are obliged to connect the uncontected ones (death of laughter) with a net to associate it with a “bogus netclass” (“we cannot separate pins from the same component obviously!”) AND still connect this net to something otherwise we still get a “not connected” error…It’s an abyss in the end.
Generally it is hard to understand for me what exactly you have in mind (too philosophical and without examples).
If I understand well this sentence I suppose net-ties are what can break writing from reading allowing to have writing net in wide tracks class while reading net in thin tracks class.
Exactly, you understood me perfectly.
What I mean with “Reading & Writing” are “atomic”, is that these 2 operations which are only the actions that WE must inevitably carry out to communicate with the world, with EVERYTHING, are “inseparable”: If I write something, it is so that it can be reread at least once, if only by myself at least. It is a rule applicable in all areas of our lives.
“Atomic” is a notion that the ancient Greeks invented to say that we cannot dissociate, separate, all of these possible constituents: This is the case for the actions of writing and reading.
Regarding the PB raised in the specific case of PCB track routing, it would have been wise if the developers had been aware that a “net” can be used “to write to something”, such as a motor pin, an actuator, but also, that this information “to be written” can also be “read” (or reread) by a control body such as a µP, and in this case, the physical characteristics of the part of the net which sends the information to to the reading device are not obviously the same since it must, as a good reading device, “take as little current as possible” from the information to be measured…
But as we can only associate here a class information with a net in its entirety, we end up with nets only used for reading with unsuitable track widths: We would therefore have to be able to break this reading atom -edition" of the net at the level of the diagram design in order to be able to indicate the portions of this net where almost no current will flow (only the insulation rules persist).
So that’s what I had to do…but it’s not very pretty, it’s a hack.
While waiting for perhaps some developer to be interested in this subject, a subject which applies from schema design, I thank you for your kind responses.
I use only Default netclass and HV (high voltage - in my case it is 24V) netclass with little higher clearance. I don’t use netclass to specify track width - I just select width on the go. When wide track I connect to pad I frequently and it with thinner segment hidden in pad just to not have the track end on the other pad side while still being connected to pad center. There was always a problem with this last segment - I had written a bug report asking to limit snapping action by screen distance to allow for stopping it by simply zooming in. I’m not sure how exactly is with that now - since 3 months I am busy with something else then KiCad.
So what you need is the “Custom rules” but these are based on distances NOT voltage simply because the pcb design only deals with distances and there are far too many factors that have to be considered
substrate material
coating vs no-coating
altitude
pollution level
Voltage from where…
since it is the differential voltage that is key, you would need to define the voltages everywhere to then have some form of rule calculate the creepage and clearance. Could it be done? of course since it is pretty much absorbing in IPC-2223, BSEN-60664, substrate key characteristics, environmental variables and additional information as to what areas will be coated…
Alot of work for the small area of power electronics (even though I would <3 it)
Thus it is the responsibility of the designer to derives distance rules for given nodes and ensure the netclasses and rules support this
Hello and thank you for your answer.
I have to tell you that I’m a little impressed: If I understand correctly, I should “write code”, know RegEx or something like that?
My job is “electronic schematic designer”, which totally boils down to “knowing how to connect a set of pins via a net”: quite simple in any case!
Based on this fundamental obligation of the profession, the only thing that would save me time, and therefore money, would be a tool that could firstly transform a net of the diagram into a copper trace.
For this, as a “cortex”, I only apply the 2 global rules of all existence: Static and Dynamic, here Tension and Current.
For the currents, the width of the track representing this set of pins, perfectly aware of the currents entering or leaving all pins of a net, since it is myself who chose the components as a good professional I hope, and This therefore constitutes the guide, the rule to apply is rather simple it seems to me.
Concerning the tensions, given that a track is an equipotential, it is simpler, and I was able to resolve the PB quite quickly with the existing one (There was still a PB with pins “not connected at all” of certain components whose clearence I had to modify, not to “0”, but to something tiny…another oddity?)
Finally, I thank you for your response, not being a “programmer”, the problem of track width remains unsolved: So we are “in the middle of the ford”, job half done?
But I remain impressed by the mass of code and time and human resources that this software seems to have required… Just a little disappointed with the result with regard to the very foundations of the profession, in particular therefore for the width of the tracks… .
I must probably be too demanding.
Have a nice Sunday.
Don’t overdo it. Just a relatively simple set of rules.
Being an electronic designer you need to cooperate with PCB designer.
You can wait few years and use AI. AI understanding your design will predict whether your product, for example, is planned to be used above 2000 m above sea level, and what pollution degree to expect where it will be used, and taking into account the voltages between the nets, by looking at the 60950-1 will determine the required distance between them. Then AI will design your PCB for you.
You don’t seem to be aware that the boards can have different copper thicknesses what influences on needed tracks width.
Just as the speed of light is not infinite, the speed of potential propagation in the tracks is not infinite and in some cases you have to take it into account while designing PCB.
I don’t know what you call PB.
And I’m delighted with the result.
You are right. You’re too demanding, especially considering the price you had to pay for KiCad.
What you think about my knowledge is your sole responsibility.
My initial question was simple: Starting from the design of an electronic diagram using components, for which we must necessarily predict the ranges of variations in voltages and currents associated with each pin of said components, can we involve these consequences in the software suite that constitutes KiCad? The answer was given to me and I thank you for it.
Now, having made this observation, drown the fish with remarks like:
“You don’t seem to be aware that the boards can have different copper thicknesses which influences on needed tracks width.” (…factor 2,3,4…price and deadlines…of course!)
or
“Just as the speed of light is not infinite, the speed of potential propagation in the tracks is not infinite and in some cases you have to take it into account while designing PCB.” (…PhyD in General Relativity, LOL, I probably don’t understand this remark…of course! My nickname “lvdl” are the initials of “Le Voyageur De Langevin”…at the speed of light! no chance ! Your number “0”, your stone “marble”… we could go on for a long time… Let’s stay serious please)
remains unproductive and rather childish.
Before moving on to the dynamic regime, it would be good, once again, to ensure the average static regime…
It’s always good to start by keeping it simple, and that’s really not what I found here… it’s so easy to drown out the fish, to tell the other person that they don’t understand anything! Words of…?
Better stop here.
its not unsolved, its just no tool knows what you are going to do with it nor how you are going to get the pcb built. You as the designer knows and thus it is your responsibility to encode this information into the tool.
This post captures the steps and it boils downto
know what current will be conducted
know the copper thickness you should use to fabricate the pcb
Determine the trace width needed to satisfy your constraints (temprise, volt drop…)
Create a netclass to set this trackwidth
assign this netclass to the traces you know will carry this current
Repeat for as many different currents you need to manage with this level of detail.
Now voltage clearance… The scripting rules that Kicad have provided are by the most flexible and most descriptive I have come across and I have used many an eCAD tool and exclusively design for higher voltages.
If the answer is that what I’m looking for doesn’t exist then that’s good news.
Some are satisfied with little, for lack of blackbirds we eat thrushes…this is not my case: All this looks a lot like Chinese Quality, which I have avoided since my childhood!
I have always preferred to do nothing rather than doing things “off the mark”.
Clearly, we will not be able to understand each other, but that is not important, it is only the reflection of a structure ready to collapse under its own weight, under its own heaviness, a colossus with feet of clay …very fashionable in these bad times.
Good luck and continuation on the path you have chosen to take.
I do not know whether this is a poor translation or you are being hostile on purpose but this is the 2nd thread with similar tone (for reference: Significations exactes des informations dynamiques d'exécution affichées dans la barre d'état de FreeRouting? )
Are you expecting Kicad to do this for you or are you interesting in contributing such capability? Because it sounds like you are being disrespectful (in this and your other thread) because a piece of software doesn’t do what you want it todo.
To tell you the truth during all this thread I am able to understand only about 50% of what you write, even using Google translator to have it in my language.
For example:
I understood only “Let’s stay serious please” from what I understand that you think that I was not serious while I was serious all the time. What I don’t understand for example is based on what you think that my number is “0”? Why you give me “0”. Do you suggest that my knowledge level is “0”?
Should I be offended or not?
And with what “we could go on for a long time”. Do you suggest that I’m talking nonsense and this way we can talk forever without explaining anything. This is how I fill this sentence.
And the same problems I have with all your previous posts. In each there are something for me looking completely senseless.
I understood:
That you assume that only static voltages at tracks are important when designing PCB. So I was trying to let you know that for many tracks at PCB the dynamic parameters (depending on signal propagation speed) have to be concerned when PCB is designed. If I understood you wrongly (which is very likely) and you know all that I assumed you don’t know then I’m very sorry.
All my answers were based on how I understand you with all the time having a fill that I don’t understand you perfectly. I’m here since 2017 and I don’t remember any such situation that everything what one is writing I understand approximately only 50%.
Hello,
I think the answer I was looking for was pretty clearly laid out here:
My problem was therefore the same and, even before finding this information, namely “connecting different net classes”, I had naturally created what apparently already existed under the name “net tied”… so, I was not an exception!
Besides, I am surprised that no one, unless I am mistaken, told me about the “net tied” symbols that I therefore created “naturally”. And I am still surprised that apparently, few people “come across this problem” which is permanent in all the PCBs that I have had to create in the exercise of my profession: Always the same PB: There are the nets which transport the energy, here intensity, track width, and those who “read” them, to control the values in transit. For the latter, a needle poking the track is what is recommended, namely, the pins of a measuring device which pumps less energy the better it is.
Yes, that’s it.
Everything is just a series of Writing~Reading events (in this direction and not the other) in space and time (A.Einstein)…
Finally, this is how I summarize all existence, all cases, all situations.
The rest is commentary, “bla bla” as they say in French.
Another question I have:
I must have seen a comment indicating that you could exclude the application of isolation rules when using manual routing, but I couldn’t find where to enforce this behavior in PCBNew? and it is necessary, including with the use of “Net tie”, except to redeclare an additional net class when the “default” class could be suitable most of the time.
Thanks in advance.
Problems with net classes:
Context: We must connect a net class 600V signal to a reading input resistor of an AOP powered at 5V. This resistance must be as close as possible to the AOP.
• PB of Insulation Voltage: see the attached PNGs: “net-tie Case A and B”
o Case A:
The “net tie” is installed on the 5V (low voltage) side:
• In this case, it is the footprint of the R803 which must support the insulation rules: For example, in CMS 1206 for 600V is suitable => OK
• But, the net class 600V will apply to the track connecting R803 to the 600V track and as resistor R803 must be as close as possible to the AOP, in most situations, we will not benefit from the fact that we can use a narrow width track to bring the 600V signal to resistor R803.
• We will therefore have a net class 600V track up to the AO p => KO
The “net tie” is installed on the 600V side (high voltage):
• In this case, we can place the “net tie” component on the passage of the net class 600V track and use a track like net class default to route the signal to resistor R803 => OK
• But, it is the footprint of the “net tie” which must now support the insulation rules: It will therefore be necessary, for example, to associate a CMS 1206 type footprint with the “net tie”, enough to lose space each time on the PCB => KO
o Unless we can exclude the application of insulation rules to the “net tie” footprint: Can we do that? if yes, where in PCBNew?
Remember: I have never used net-tie in any my design… so can be wrong with my assumptions.
Case A.
In my opinion using N1 makes no sense - there are no reason to have both its sizes to belong to different net classes.
Case B.
I don’t understand why you think that net tie must support insulation rules - its both sides are at the same voltage - they need not be isolated.
N1 only makes sense if there is a reason to have Va wide when then connection to R803 thin. But I don’t use net-classes to specify track width. I just use track width as I need not looking at any net class settings. So if it were my design I would not use net-tie here.
As both sizes of N1 are at 600V then both have to have higher clearance than other nets so both sides should belong to same net-class to specify higher clearance. If both sides will be the same net they also (being one net) will belong to the same net-class so N1 is not needed.
Conclusion.
If it were my design I would not even considered to use net-ties.
Just Va I would assign net-class with higher clearance then for the rest of design.
now I am concerned you are saying the pad-pad spacing of a 1206 is enough… IPC2221 has 600V uncoated at sealevel to be 3mm (1.1mm for coated) a 1206 resistor has a pad-pad of 1.7mm
lets assume you are doing coating then you set the rule to be > 1.1mm for HV-LV and the tool will do the vast majority of the work for you… BUT you need to set the distance and you need to assign the nets as there is no way the tool knows what you are doing…
