How do I use net names to uniquely label massively repetitive circuit designs? I have a way that almost works, using sheets that fold/unfold busses, but it doesn’t seem to be a kosher solution given the side-effects I’m seeing. Here’s my schematic for reference:
My process so far includes making judicious use of hierarchical labels and repeated sheets to:
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Attach a “Folder” sheet to each triad of input pins (
+,-,GND)
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Run that bus to the sheet with repetitive elements (in my case, filters for 16 differential channels)
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Use an “Unfolder” sheet to route wires to output pins
This mostly works (with side-effects: net names come from the alphabetically sorted unique name of attached elements, and nets are sorted in non-Windows fashion so net /2/... comes before /10/..., so name your repetitive sheets A-Z and everything else with a later-sorted character (e.g. brackets []), however the ERC warns that the labels aren’t connected to anything in the folders/unfolders (which they’re not, they just unfold the bus). Other tactics like unfolding the bus in the main sheet don’t work since the unfolded labels will be redundant (error: label not a member of the bus, because the bus actually contains labels like <Prefix>_1_2_3_4_5_6_7_8.<Suffix> i.e. Eescheema tags on underscores and sequential numbers to uniquify labels)
Enhancements Requested
If what I’m doing is crazy, appreciate the guidance, otherwise here’s what I’d propose changing/fixing:
- Allow redundant labels in the same hierarchy level, so long as unique nets can be established
- Allow manual prefixing of nets originating from some hierarchical sheet (or some setting to control inheritance or something)
- Fix label expansion uniquifier to append an incrementing number, not just more numbers (literally right now, each of my hierarchy sheets has busses coming out with labels like
AI.F+,AI_1.F+,AI_1_2.F+, …,AI_1_2_3_4_5_6_7.F+, not like justAI_12.F+, which would make more sense).