I haven’t gone very far down that road. I think you get a (usually proprietary) “mixed-signal simulation program”, or study up on the SPICE “extensions” available on some of the no-charge SPICE simulators (including, if I recall correctly, NGSPICE).
Dale
Dale, Holger, or Massimo, if you were at KiCon, my apologies for not meeting you. I was one of the people behind the bar serving breakfast/lunch and servicing the drink cooler.
Yep - for quickie logic simulations as well as power supply sims I go to LTSpice. I’d love to go to Kicad… That is what I’m working on.
Unfortunately, I was NOT at KiCON. I certainly wanted to be there, not only to support Chris’ initiative and express some appreciation for all of his work, but also to attach some faces and voices to ID’s here on this Forum. But even though Chicago is an easy train ride from St Louis, KiCON didn’t fit into the budget for the Working Poor.
Dale
P.S. - I’d like to say, “I’ll be there next year”, but my wife’s medical situation will probably keep me on a pretty short leash for the next few years.
Dale, I understand your situation.
Yep, I appreciate Wayne, Chris, and all of the developer’s efforts. And want to give back in my own way. I use this program a lot in my daily job.
Holger - thanks - this is looking familiar to what I remember of the xspice source code. I’m probably going to start looking at the kicad/xspice interface and libraries under the rationale of getting my day job done… I’d love to stay in kicad and not flop out to ltspice.
That’s ok in the schematic perspective. I was thinking to have a lib file containing some resitor models. For simplicity think to have just one resistor model inside the library (suppose the model for a SMT 0402 resistor). The temperature coefficients and the values for parasitics R, L and C are not dependent by the resistor value but from its physical structure and its material so, passing the nominal value between the symbol Value and Spice Value makes sense. In this way I could have just one library file containing the Spice .subckt describing every SMT 0402 resistor and I can simply link the .sunckt with each resistor symbol I need using the Symbol Editor.
No, I was not there.
I believe we met at KiCon, but you had to duck out early because you weren’t feeling well. Hopefully all is good now!
In the SPICE talk at KiCon, I tried my best to cover (in the short amount of time we got) how to set up a real-life schematic for simulation. The ideal, as you hinted at, is to have a single schematic set up for real-world construction and simulation at the same time. I think this will eventually be 100% possible within KiCad. You can probably do it now, but it requires a bunch of goofy workarounds.
For opamp models, I definitely agree with you that it’s very handy to be able to change the complexity of the model depending on what you’re trying to investigate. I usually start with ideal single-pole models for filter design, and then move over to more complex models (usually provided by the manufacturer) to validate the design further. I really like LTspice’s “UniversalOpAmp2” model/symbol because it somewhat encapsulates your vision here. You can select from 4 different model types each with increasing complexity. The differences between each level are explained in one of the example projects included with the program.
I would like to return the discussion to the specifics of EESchema / KiCAD netlisting and how to flow parameters / expressions down to the lowest layer of the circuit, from above (make that an arbitrary number of levels above).
Take for example a top level schematic with N subcircuits; subcircuit A contains another subcircuit M which contains a transistor pair whose Ws we want to vary (think of an inverter primtive with parameters WP and WN for the PMOS and NMOS). Subcircuit B also contains an instance of subcircuit M where we would like to have the transistors differently sized.
XA D CK Q vdd vss myDFF {?forWP(A)} {?forWN(A)}
…
XB S R Q vdd vss mySRFF {?forWP(A)} {?forWN(A)}
…
.subckt myInv Y A vdd vss {?passedWP} {?passedWN}
MP Y A vdd vdd myPMOS w=WP1E-6 l=0.5E-6 m=1
MN Y A vss vss myNMOS w=WN1E-6 l=0.5E-6 m=1
.ends myInv
.subckt myNand2 Y A B vdd vss {?passedWP} {?passedWN}
.subckt mySRFF Q S R vdd vss
XSb Sb S vdd vss myInv {?passedWP} {?passedWN}
XRb Rb R vdd vss myInv {?passedWP} {?passedWN}
XQ Q Sb Qb vdd vss myNand2 {?passedWP} {?passedWN}
XQb Qb Rb Q vdd vss myNand2 {?passedWP} {?passedWN}
.ends mySRFF
where all the {?} are where I need syntax guidance to pass
through and/or tap the values that came down from above
Does anyone have an example netlist to share that shows
an effective and regular way to do this?
I was given some advice about how to do the passing in of
MOSFET W, L, etc. on a single FET’s element line by making
the last “canned” parameter of the symbol a concatenation
of multiple params as text. But I would like to generalize it, such
as:
how to add params to a subcircuit and make netlisting “see”
them and pass them in literally (not evaluated until the bottom
is reached)
how to “shield” params from any conversions like string to float
how to force conversions of params from string to float or do
local string*math ops to create scaled or function-call args that
use passed params without munging the pass-down
I couldn’t find this kind of info in the docs and this is what’s
bounced me from EEschema as an IC design schematic tool.
I like the UI but what goes on behind the curtain, I need to
understand
Check out section 2.8.3 of the ngspice manual for subcircuit param examples.
For the hierarchy stuff you’re talking about, I believe you need to do something like the below. Hopefully there are no name conflicts, otherwise you might have to give different names for the parameters on each level of this structure. I’m hoping it works like this, but I don’t have time to test it out for you.
.subckt mySRFF Q S R vdd vss pwidth=1u nwidth=1u
XSb Sb S vdd vss myInv pwidth={pwidth} nwidth={nwidth}
XRb Rb R vdd vss myInv pwidth={pwidth} nwidth={nwidth}
XQ Q Sb Qb vdd vss myNand2 pwidth={pwidth} nwidth={nwidth}
XQb Qb Rb Q vdd vss myNand2 pwidth={pwidth} nwidth={nwidth}
.subckt myInv Y A vdd vss pwidth=1u nwidth=1u
MP Y A vdd vdd myPMOS w={pwidth} 1E-6 l=0.5E-6 m=1
MN Y A vss vss myNMOS w={nwidth} 1E-6 l=0.5E-6 m=1
.ends myInv
.subckt myNand2 Y A B vdd vss pwidth=1u nwidth=1u
…
…
.ends myInv
.ends mySRFF
XB S R Q vdd vss mySRFF pwidth=3u nwidth=4u
where the “pwidth=3u nwidth=4u” are the desired sizes for that particular instance of “mySRFF”, and “pwidth=1u nwidth=1u” in the .subckt lines are your defaults for when all those things are instantiated without any parameters specified.
Thanks, Ste,
This looks good, for once you’re inside NGSpice. My KiCAD
question is, how to make a symbol which has those properties
and will create the SPICE netlist line(s) with that syntax. I was
shown the approach of making the last existing property in
the existing set of a MOSFET primitive, a concatenation of
all the args needed but that is not really clean IMO. Do you
know where (or if) a description of how to add symbol properties
and control their netlisting can be found? I couldn’t find it in the
KiCAD help.
Like suppose I wanted to copy the standard MOSFET symbol
to my local “PDK” library and add L, W, M properties and make
these, numeric or variable-as-string, flow down to the SPICE
deck. How to add the properties, how to make my own symbol
netlist in its own way and the property of a higher level symbol
flow through and to lower level ones, in the EESchema domain
so that the low level devices get what they need?
I think you want something like this. This was slapped together pretty quickly just to highlight what’s available. I used an opamp symbol because it has 5 port pins, and I didn’t want to draw something custom. Resultant netlist is attached. Every node hanging off a symbol needs to be connected somewhere otherwise the SPICE netlist generator with make them NCs, even if they are labeled. That’s why I hooked up a bunch of sources and a load. This annoying behavior is not common to other SPICE programs.
The key is changing the “Spice_Model” field and you can also check the box so it shows up on the schematic for easy editing later. I am unsure if Eeschema can handle newlines so you can format that field nicely if it’s very long and has tons of parameters you want displayed.
srff.cir (175 Bytes)
Hi J, do you have any suggestion about how to simulate an I/O pin of a microcontroller? If you look at LPC8xx family by NXP you will see that as output at VDD=3.3V the VOH may vary between 3.0V and 2.4V depending by the current and temperature.
Hi Massimo, it depends on what effects you are concerned about. The VOH variations are due to the RDSon of the p-channel mosfet that is driving the high output.
I can suggest two approaches depending on how accurate you want to be: 1) build an output stage with generic nmos/pmos with resistors in the drains, or 2) build an output stage with 4-terminal nmos/pmos models from another foundry and fit L and W to match the expected RDSon.I think the output stage is sufficient. I may have 2 different subcircutis one for push-pull output mode and the other for open-drain mode. What I would like to have is a model that takes care of the output current so that VOH is dependent by it and then would be nice to have also a way to take care of the temperature effects.
I definitely agree with method-1 and method-2, but I would like to also propose method-0 and method-3 to be comprehensive:
0 - Build a thevenin equivalent circuit, i.e. just an ideal voltage source and series resistor. I usually construct this by measuring the output unloaded and then once again under a load that fits my operating conditions. Then you can calculate Vt and Rt from this data.
3 - See if IBIS models are available from the manufacturer. You can use a tool to convert them into SPICE subcircuits. I actually just made a post about this: IBIS models within ngspice/KiCad
I typically use method-0 and method-1 the most frequently since they are the easiest to deal with and give very good approximations for my typical applications.
Thanks Ste. Good advice.
Jim
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