I’m using KiCad 6 and as you can see in the schematic, I’m failing the rules check because the output pin from the inverter is setup as open collector and isn’t driving the input pin of the '244. I’m not sure how to fix this problem other than editing the “built in” components and changing it to an output. But that doesn’t seem like a clean solution considering these are the standard components.
Any ideas on how I can handle this?
BTW, I’m taking this schematic from the excellent book Microprocessor Systems Design. I thought about maybe putting a pull-up on that line but the original schematic doesn’t have it.
Those rounding errors are quite important, as messages posted on this forum will be kept, be visible and searchable like “forever”. KiCad V6 was expected early this year, but at the moment it would make a lot of people happy if it’s released before the end of this year.
What source? What book?
The theory is pretty simple. Open collector outputs switch between “floating” and pulling to GND, and TTL inputs should never be left floating, and there must be plenty of other sources where you can verify this.
Un-driven TTL inputs generally pull themselves high due to the internal structure of the IC. This is not a reliable design, however, especially at higher switching rates. Modern ICs based on CMOS technology have unpredictable behavior when an input is not driven. If you substituted a 74HCT244 for the 74LS244, the circuit would likely fail without the pull-up resistor.
I did some experiments using the textbook “Digital Computer Electronics” by Malvino and Brown. Originally published in 1977, and updated in 1983 and 1993, this book is out of print but still available on the used book market. The design works as described, but when configured to load a program into the RAM it enables two tri-state outputs to drive the data bus at the same time. It’s good enough for an experimenter’s project, but it’s a serious error nonetheless.
Here’s a link to my blog post describing this design error in detail: click
From what I remember of those old things this was considered a bad habit. It works on your bench, and later in the field you have intermittent problems. A partial blame on PCB design habits of those day’s with dual layer PCB’s (horizontal and vertical layer) and no proper GND plane.
My own experiences with AVR controllers are also not great. The reset pin of an ATMEGA8 has an internal pullup, and especially if when wires are connected (reset button in accessible location, ISP connector (not even a cable!) and build the thing on Matrix board, you can get occasional / random resets. After I discovered that I always added an extra pullup and a small capacitor to suppress glitches (So it’s not the RC constant to create a long reset time which used to be common). Just like regular decoupling caps, I put this capacitor close to the IC (although less critical).
74LS05 Fairchild data sheet explains the necessity for a pull-up resistor and gives the formula for calculating, but why not use a normal output 74LSxx inverter?
Alright, got off my posterior and did a one minute search: 74LS04 has the same package and pin connections but the six inverters are standard TTL outputs… not open collector. Substitution will solve the problem?
I think I see what the problem is. The schematics I was looking at were on two different chapters. On the first, it was a “high level” schematic that indeed used a 74LS05. But that 74LS05 DID have pull-up resistors like it should have.
Then, several chapters later, there is a more detailed schematic. However, it’s still a “high level” and not all parts are even identified. This schematic shows an inverter symbol but doesn’t label it an 05 or 04. So I assumed I could just use the leftover gates.
Long story short, it’s quite possible the second schematic would probably use a 04 instead of an 05.
So now I’m wondering why they used the 05 in the first place and not an 04. I’ve got lots to learn and this is a pretty large book.
As davidsrsb says, active high wired AND or active low wired OR. Also used to drive indicators. Before LEDs incadescent displays were driven by OC outputs with higher voltages than the main supply. Look at the 7406/07/16/17 ICs. The concept carries over to open drain for FETs. Look at the TPIC6B595 for example.
(I used to work at Racal Milgo in UK, back in 80s): yes, I remember those busbars, and back when you had rows of 0.3" chips, were a good way to get the power distributed… and yes, probably a lot cheaper than going to 4 layes - especially back then!
Why use a 74LS chips at all, because those ICs are available in 74HC series and much more, like 74HC40 and 74HC45 series. Or they were available because world has moved on, and those chips are used less and less every year.
Caveat: if you replace only some LS with HC check all the places where LS drives HC because LS logic 1 isn’t quite high enough resulting in lower noise margin. So either replace all or if must mix use HCT which is designed to cope with LS levels.