DRC will not shut up - SMD footprint has internal connections

[mr_bandit]

I have a TSSOP-20 package. If I do a very simple schematic, just the chip and 1x10 berg connectors (Pin 1x10) on each side && connect with 10 mil traces - golden - DRC is happy.

I do need to set the min distance is 7 mills - the pitch of the pads is 25 mils and the pads gap is 7 mils. Note: If the min spacing is set to 10 mils, DRC is unhappy with all pads - but happy with 7 mils. Cool - that makes sense.

However, in my real pcb layout, DRC is always unhappy with three pads. They appear exactly the same as the others, with one interesting exception:

Look carefully at pads 14-17 (circled). To their left is a thin red line that seems to connect them together. The DRC reports the following. Note these are on non-copper layers. I also get the white arrow markers

(The test schematic was exactly the same, but wired directly with the 1x10 headers instead of buses.)

I have conducted a number of experiments to try to figure out what is going on. No joy. One was adding my little test of the chip and two 1x10 thru-hole berg connectors (pin 1x10). I was able to layout that chip/connectors on the same PCB as the odd ones - everything was cool on the test chip and the usual errors on the originals. The test footprint did not have the funky thin red lines for pads 14-18. I cloned the good one, deleted the old one, and renamed the clone as the deleted one - the re-named clone was instantly was turned into the dark side.

Another test was to look at the pads at different levels - specifically the non-copper layers. They all looked fine.

One time, I was able to get kicad to be good. Not sure what I did, but it did not last. This is what “good” means - pay attention to the thin red lines.

I looked at the netlist, the kicad_pcb, footprint, and the other related files - things made sense. The red wires are not in the footprint file.

One possible hint: The first time I created the footprint and imported it, I got the origin wrong (way off). I deleted that and redid the chip origin. I then used the correct footprint exclusively and the origin was correct (I was able to move he chip relative to the new origin).

I would like to upload both the library and footprint files, but, as a new user, I am not blessed. However, they are basically clones of the TSSOP-20 with a new name and new pad names. Nothing in the description/definition stands out.

[hermit]

@mr_bandit

Look carefully at pads 14-17 (circled). To their left is a thin red line that seems to connect them together.

That looks like clearance lines. Open the footprint in the editor and check them there.

[Rene_Poschl]

Just to add to that, clearance can be set at multiple levels.

• The highest priority is the setting of the pad.
• One priority lower is the setting for the footprint.
• The pcb setting has the lowest priority.

To tell kicad that you want the settings of one of the lower priorites you need to set the clearance in question to 0.

Both the footprint and pad settings can both be set in the library (via the footprint editor) or in the placed footprint (inside pcb_new).
However setting for the placed footprint (or pad) inside pcb_new does not change the footprint in the library.
The same is true the other way round as footprints already inside the pcb are not automatically updated from the lib.

[paulvdh]

My immediate thought was also about clearance.
Sometimes hard to distinguish all those layers.
If you have any doubt, which is on what layer you can turn layers off, or even generate gerbers to look at what exactly is on which layer.

[Sprig]

With so much other detail in your post, you managed to never tell us what Footprint model you were using.

All of the Pad clearances are wrong.

It does not seem there is enough information presented to determine exactly where the issue is.

[mr_bandit]

I started with the TSSOP-20 footprint.
I tried attaching the model, but since I am new here, it would not allow me.

Not sure what you mean by “All of the Pad clearances are wrong” - they are spaced 7 mils apart, and as long as my minimum distance in the general Rules is set to 7 mills, the rest of the pads are OK.

I also started with a library footprint and just changed the name of the component and the names of the pads. I did not touch the spacing.

[Rene_Poschl]

When we talk about clearance we do not mean spacing.

The clearance is a setting of the pad that determines how near copper features connected to a different net are allowed to be.

As i said above there are multiple places where you can set this clearance.

---

The highest priority is in the pad setting of each pad. This can be changed via the pad editor. To change it on the library level use the footprint editor. To change it only for your current project open it via pcb_new. For both the user interface is the same. The dialog is opened via shortcut “e” while your mouse is above the pad in question or by rightclicking on the pad -> edit.

---

The next option is within the footprint it self. If you set the clearance of the footprint all pads of this footprint that have their clearance set to 0 will take the clearance of the footprint. (Tested in both nightly and 4.0.6)

---

The final place is on the net level using the net class settings.
This again only affects pads that have no clearance set in the pad setting or in the footprint settings.
The net settings can be changed in pcb_new->design rules->design rules

---

So there are a few things that might have gone wrong.

• The 3 pads have clearance set
• The 3 pads do not have clearance set and the footprint clearance is set (or your net clearances are set higher then all the other pads)
• The 3 pads are connected to nets with a higher clearance then all other pads

[1.21Gigawatts]

Pads 15 & 16 of U5 appear to have incorrect clearance settings, regardless of how that may have happened. If you haven’t already, read what @Rene_Poschl says above and check the per pad settings for those two pads.

[mr_bandit]

I opened the footprint editor. Here are the results (I will try the above suggestions after this…) Please notes this is the library version, not the ones on the PCB itself -

Footprint properties:

and the pad - this looks good. The local clearance and settings are all 0’s.

… bandit

[Rene_Poschl]

In your second screenshot you show the wrong tab. click on Local Clearance and Settings to reveal the same settings as you see in my annotated screenshot.

[1.21Gigawatts]

@mr_bandit

Please notes this is the library version, not the ones on the PCB itself

It’s strange that the library footprint would have a Reference value of ‘U8’. But we are more interested in the properties of the footprint on the board for U5.

[Rene_Poschl]

@1.21Gigawatts

It’s strange that the library footprint would have a Reference value of ‘U8’. But we are more interested in the propertied of the footprint on the board for U5.

I would guess he opened the footprint editor from within pcb_new when he originally reworked and saved it into his personal lib. That way one gets the reference equal to whatever value the footpirnt had that gets opened that way.

@mr_bandit
A better way of doing it is opening the original footprint inside the library either via the library browser or by setting the source lib as active and searching in there. (list all or by keyword)
Maybe this FAQ post can help: Creating a new footprint library

[mr_bandit]

Rene Poschi:

You provided the key. THANK YOU…

I changed the design rules to

I had the “power” at 0.010 (10 mils).
Changed it to 0.007 && had a clean DRC.

I would buy you a beer - keg sized - if I could.
I have used CircuitMaker and TraxMaker for 20 years, and Altium for about a year. The switch to Kicad has been … interesting.

And - it has been my experience that the problems like this (almost) always takes 3 days, and the solution is always a setting, or a couple of lines of code, etc… I have forehead shaped holes across the country from these types of problems.

Well done, Sir!

Thanks again! … bandit

[hermit]

@mr_bandit

I would buy you a beer - keg sized - if I could.

Well, maybe not a direct contribution, but…
https://giving.web.cern.ch/civicrm/contribute/transact?reset=1&id=6

[mr_bandit]

Excellent Suggestion.
Thank you! … bandit

[Rene_Poschl]

Or help out over at the library by taking on one of the open issues

(Man i hate the recent github redesign. There is no nice way of listing all open issues of an organization any more.)

[1.21Gigawatts]

@mr_bandit

I had the “power” at 0.010 (10 mils).

That makes sense, I would have expected that to have affected more than just those pins. Glad you found the issue.

[mr_bandit]

The 4 affected pins were signal, gnd, vcc, signal - basically power and the ones on either side. That should have provided me with the real clue. Although I have used Altium and other professional schematic/PCB tools, I am (still) a newbie to Kicad && still learning how to think like it.

Is it possible to mark this closed instead of waiting 3 months?