I have a TSSOP-20 package. If I do a very simple schematic, just the chip and 1x10 berg connectors (Pin 1x10) on each side && connect with 10 mil traces - golden - DRC is happy.
I do need to set the min distance is 7 mills - the pitch of the pads is 25 mils and the pads gap is 7 mils. Note: If the min spacing is set to 10 mils, DRC is unhappy with all pads - but happy with 7 mils. Cool - that makes sense.
However, in my real pcb layout, DRC is always unhappy with three pads. They appear exactly the same as the others, with one interesting exception:
Look carefully at pads 14-17 (circled). To their left is a thin red line that seems to connect them together. The DRC reports the following. Note these are on non-copper layers. I also get the white arrow markers
(The test schematic was exactly the same, but wired directly with the 1x10 headers instead of buses.)
I have conducted a number of experiments to try to figure out what is going on. No joy. One was adding my little test of the chip and two 1x10 thru-hole berg connectors (pin 1x10). I was able to layout that chip/connectors on the same PCB as the odd ones - everything was cool on the test chip and the usual errors on the originals. The test footprint did not have the funky thin red lines for pads 14-18. I cloned the good one, deleted the old one, and renamed the clone as the deleted one - the re-named clone was instantly was turned into the dark side.
Another test was to look at the pads at different levels - specifically the non-copper layers. They all looked fine.
One time, I was able to get kicad to be good. Not sure what I did, but it did not last. This is what “good” means - pay attention to the thin red lines.
I looked at the netlist, the kicad_pcb, footprint, and the other related files - things made sense. The red wires are not in the footprint file.
One possible hint: The first time I created the footprint and imported it, I got the origin wrong (way off). I deleted that and redid the chip origin. I then used the correct footprint exclusively and the origin was correct (I was able to move he chip relative to the new origin).
I would like to upload both the library and footprint files, but, as a new user, I am not blessed. However, they are basically clones of the TSSOP-20 with a new name and new pad names. Nothing in the description/definition stands out.