I’m designing a very simple PCB which consists of only one single component in the schematics - a battery mating connector with spring pins (SMD). The purpose of the PCB is to break out the four mating pins each to a 1mm hole via so I can solder and connect AWG 22 wires.
I drew the vias in PCB Editor and manually assigned each via hole with the Net corresponding to the pad’s Net. Then I drew a 0.5mm trace to connect each pad to the via holes. As simple as that. But when I ran DRC, I got this warning:
Warning: Via is not connected or connected on only one layer
How is that possible? The vias should be plated on the inside wall, connecting F.Cu and B.Cu around the hole. A trace from the pad to the F.Cu of a via should electrically connect the other side of the hole on B.Cu.
The only way to resolve this warning is to draw and fill a zone around each via, but that doesn’t make sense to me. I don’t need to pour any ground or power plane, but simply to break out the pins to solderable via holes. Also, the PCB only has two copper layers and has no more layer left to “fill”, other than “filling” the area around the annular ring on the same and overlapping layer, which doesn’t make sense to me either.
Could someone help explain why filling the zone around the via (or around the annular ring of the via) works, and is it really a proper way to do my PCB? I’m still fairly new and inexperience in physical PCB design.
In this case the warning is telling you exactly what it means: it is only connected on the top with
the traces you drew. Normally vias should be used to connect 2+ layers, so KiCad brings this to your attention in case it is a mistake. You appear to currently have no copper on B.Cu except the via annular rings.
One underlying confusion here is that while vias can be big enough to solder to, generally you should place or make a connector footprint with plated through hole pads. While through hole vias and plated through hole pads are physically similar, they will be treated differently by manufacturers and KiCad (especially related to solder mask). As a general rule, vias are often drilled by smaller bits and require smaller annular ring compared to connectors / bare wire / components.
Scone explained it pretty well. Via’s are for connecting other items on other layers, so KiCad expect a via to connect to “something else” on at least two different layers.
In your case, use a footprint with THT holes. I don’t know your pitch, but KiCad has footprints for connectors for a whole lot of different pitches. You can (and it’s fairly common) to use a footprint for a 2.54mm header and then solder the wires into those holes.
Thanks. Yea everything works once I build the a single footprint for the breakout vias. Strangely enough I also need to add the symbol it to my schematics have the wire drawn as if it’s a component or else the PCB Editor won’t allow me to manually select a Net or draw any trace connecting to the via holes.
Why do you think that is strange? If the connections are not in the netlist, then KiCad won’t let you make faulty connections, and you create the netlist by drawing the schematic. That’s standard lesson 1 with learning any PCB design program.
