Could anybody explain what technical reason is for such DRC rule? I have drawn lots of parralel tracks on my board, space between tracks is always within DRC limit, but on some random places I got warning about this rule.
depending on your grid size its likely that there is a tiny segment at the end of that trace that is too close, on the left hand bar is a red / green cross called “display traces in outline mode” will likely reveal to you what is going wrong.
It appears the trace avoidance rounds down, while the DRC checks the actual value.
Sometimes if it is very close to the limit, the interactive router and the DRC check differ in opinion if it is acceptable. (Might be some sort of rounding error.)
I have discovered the root of my problem. Spacing between pins of chip were little random at some digits far after decimal points, so if tracks were anchored at pin, routed in parralel and then bend, only on some tracks showed this error.
But my question is still open, DRC rules ussually comes from some limitations of manufacturing process, in case of this rule, should it be understand as “to small clearance” or something else?
I assume it should be interpreted as too little clearance. Look at the detailed drc message. I assume it talks about two different nets.
HI ! I got this error indication on on occasion. However it was logically correct it turned out to be a bit “missguiding” as to the “expressed cause”. It turned out that the pad to which the wire was wired were of another NET ! (something had gone wrong in some stage, dont ask how or why), so changing the pad to the right (same) net resolved the issue. But then I have also “cracked” the relation between the schematic part and the pcb. so I now only edit the pcb part in pcbnew, never import a new .net file. (too much work to try to correct the relation, and too much work invested in the pcb layout)
If the schematic net differs from the pcb net are you sure it is connected to the correct things on the pcb?
Kicad determines what net belongs to what trace by walking along the trace starting from a pad. (It gets the net of that pad) So if a trace has a different net to the pad it seems to be connected to, it got that net from another pad that has a different net. Normally this would mean these two pads should not be connected. (Or they are not connected according to the schematic.)
Well yes and no. As things went down; I had finished the design, all wiring done, and routed on the pcb (a one layer design, so there was a bit of work put into routinig). Then I wanted to add a componenent, and did that on the schematics layer, however I had also put some footprints directly onto the pcb in pcbnew, and when I applied the new netfile in the pcbnew things got away, so I had to rerert to a somewhat older version of the pcb. When I did check that with DRC I got one single “track too close”. checking it out I saw that it was a wire that was going where it supposed to, but the origin net-name was no longer the net of the target pad. Which of cause is in a way “too close” since they were connected. And NO i have yet not solderd the componentes and tested the pcb, so Im not 100 sure that it was right amendment. BUT essentillay my remark here in the discussions was to point out that this “mysteriously appearring” error text of DRC can be due to differing net on target versus origin of a wire, is is possibly not the immediate think one does getting the error
Your stuff would be easier to read if you would put in some empty lines.
When importing the netlist you can choose to keep footprints that are not in the schematic.
You can also lock footprints that you wish not to be removed. (I use this for my mounting holes, symbols and for all “stitching via single pad footprints”)
That way you can keep the schematic and pcb in sync and have the support of tools like DRC to ensure that everything is correct.
[quote=“georg, post:8, topic:7790”]…however I had also put some footprints directly onto the pcb in pcbnew, and when I applied the new netfile in the pcbnew things got away…
I hate to say it, but print out the traces on the file that you think worked, and start over with that print in hand as a reference to save you time in the re-work.
The only loosely termed “footprints” that I would put directly on PcbNew are holes.
It does not take that long to start out new with a fresh canvas free of quirks.
Yes thanks, I get that now. It’s kind of learning cost I guess. Btw, thanks Rene, will try keep some air in the text.
And OK, I will do some experimenting, but I think my current design is kind of hard to save the the pcb layout, but for what Sprig says; start over from net, and use a “printout” for handmaking the same pcb routing over once again.
I think my main misstake was to first insert some “for future development” foot prints (unconnected on network); first on the pcb, and then to make it “more correct” tried to include on the network level, things really got out of hand; where annotation re-annotated (at least what I think) some components. So I got a reall spagetti of “wires to make” on the pcb when importing the netlist. I think alls is fine now (however realy test from mounting is still to be).
And the design is lost for the moment on the schematic level. (some day …)
I don’t think you could possibly make as big a mess as I made while learning KiCad. If you did make a bigger mess, you deserve a medal!
I know that right now you are frustrated by the thought of starting over. But, if you know your files are corrupted, you are best to start over.
And, trust me, it won’t take nearly anywhere near the time to re-create problem free files as it did to screw them up the first time!
In addition to my messing up on Kicad, In some way my Outlook (yes I dont like that one) has decided to hide my incoming emails (suddenly grouped on “converstaion”) so I have missed a trivial question from pcb-producer in Kina. Now at last finding out why nothing happens (darn xx@@ !!) Kina has an 8 day national holiday where nothing seem to happen …
It does seem a bit bleak just now.
Needed some encouragement