DRC shows Error Filling Groundplane

I have attached a completed circuit. I looks to me as thought the ground plane is contiguous where needed and there should be no DRC errors (for List Unconnected). Nonetheless I get errors. Seems like the areas in question are well connected.
Any ideas?
thanks
Fritz

I’m not seeing an attachment.

circuit.zip (52.5 KB)

I’m getting no errors.

FWIW, there is a thin trace segment between two thick ones near Q4 pin 2. On purpose?

Application: Pcbnew

Version: (5.99.0-8300-gfc7f1d1d86), release build

Libraries:
	wxWidgets 3.0.5
	libcurl/7.71.0 OpenSSL/1.1.1g (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.3.0 libpsl/0.21.0 (+libidn2/2.3.0) libssh2/1.9.0 nghttp2/1.41.0

Platform: Windows 10 (build 19042), 64-bit edition, 64 bit, Little endian, wxMSW

Build Info:
	Date: Jan 10 2021 22:02:06
	wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8)
	Boost: 1.73.0
	OCE: 6.9.1
	Curl: 7.71.0
	ngspice: 32
	Compiler: GCC 10.2.0 with C++ ABI 1014

Build settings:
	KICAD_SCRIPTING=ON
	KICAD_SCRIPTING_MODULES=ON
	KICAD_SCRIPTING_PYTHON3=OFF
	KICAD_SCRIPTING_WXPYTHON=ON
	KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
	KICAD_SCRIPTING_ACTION_MENU=ON
	KICAD_USE_OCE=ON
	KICAD_SPICE=ON

In KiCad V5.1 (The current stable version) the poured zone can not reach the center of pad 2 in the top SMT footprint because the track "Net-Q3-Pd3) is too close to the pad for the current clearance settings, and therefore treats it as “not connected”.
image

If you select the zone (by clicking on it’s boundary) then press e for edit and change the clearance from 0.508mm to 0.4mm, the errors disappear:

image
Note that now the spokes on the left and right are also fully formed.

But you have a much bigger problem.
The goal of a GND plane is not to make more “red”, but to make make good connections between all nets connected to GND, and to provide return paths for currents very close to the signal paths. In your design you have neither. your GND plane is completely cut to pieces by the copper tracks on the top side, while the bottom of the PCB is nearly empty:

So I took the liberty to change your PCB a bit.

  1. Move the GND zone to the bottom of the PCB.
  2. Pcbnew / File / Board Setup / Design Rules / Net Classes Set “Trackwidht” for default net to 0.635mm. (That is the track width you seem to prefer).
  3. Move most of the tracs on the bottom layer to the top, to make the GND plane more continuous.
  4. Add via’s to the GND pads (SMT only) to connect them to the GND plane on the other side of the PCB.
  5. Pcbnew / Edit / Cleanup Tracks & Via’s
  6. Run DRC.

The PCB now looks like:

Those were just a few quick fixes. The two “bridges” on B.Cu can easily be removed by changing the footprint layout a bit and you may want to add mounting holes or move the 2 pin connectors further from the edge to make them less vulnerable.

I also noted you have a netlist file, which is a bit old school. Try to use Eeschema / Tools / Update PCB from Schematic [F8] which has the same functionality, but does not make a netlist file, and it directly synchronizes the changes into Pcbnew.

Also: Next time do not change the folder name to “circuit”, but just leave the original name. I’ve got 10’s of projects called “circuit” “pcb” “example” and other such names…

@straubm Don’t mention nightlies when a user asks a question about a project that is made in KiCad stable V5.1.x.

Here is the modified project:
pulse1.zip (20.6 KB)

1 Like

@paulvdh

How should I know? It was not stated, or did I miss something? I included my version, so it was clear what I was referring to.

It was not explicitly stated, which means the default for you should be the stable version. On top of that, the project opens in KiCad V5.1.x and this can not read files from KiCad-nightly V5.99, and the files also have different extensions for V5.99.

Thank you for the comments Martin and sorry for not including my rev numbers etc–i usually try to do this (was a long day!).
The thin trace segment was not intended–i was in the process of sketching up this board for an “emergency” and had not checked it once I got the ground plane error and wanted to stop there.

Two questions regarding revisions–

  1. I like your presentation of the rev numbers-is there somewhere to get this with one shot in the form you show? The “about” command does not do all this for 5.19
  2. I would like to try 5.99. It is not clear to me but I don’t think I can run a separate version alongside 5.19 on a win10 machine. Is this correct? I do have a version up on an older machine. Also I wonder if 5.99 is backwards compatible with 5.19 if I “get into trouble”.

Cheers
Fritz

Paul–I appreciate all the time you spent on this!
Your comment on the on the failed fill for pin 2 is well understood. Looking at it I usually do not like traces in between pads with such close tolerances (am I overbearing here?) so I would typically move it rather than decrease tolerances (I am never sure how dangerously close I can get with varied board cutters).

Regarding the poor grounding of the overall system, I understand what you are saying and have an awareness here but I am never sure “how much is enough connection” etc. Your remake of the board is really helpful for gaining understanding here. I have found occasional comments on this and similar topics in books and the web but I have never really found a good book that helps people like myself move to a higher level of design. (I work primarily as a physicist and learned electronics largely from my own reading over the years).
In the past I have used a lot of 4 layer boards–a way to slip by some problems–but cost and especially shipping times encourage 2 layer. I am aware of the theory of issues with both regarding interplane capacitance, and for RF designs, signal distance–but good books on this are rare unless I missed them. Other issues such as board compactness are one of my weaknesses. I see very simple poorly laid out designs on the web and then very comples 6 layer ones, but I am largely up to my own devices getting a good layout.
Many thanks again for your time!
Fritz

You can install V5.99 alongside V5.1.x and you can open old projects in V5.99, but once you saved a project in V5.99 there is no going back to V5.1.x for that project because file formats (especially Eeschema) have changed a lot and there is no converter (yet?) to read those files in older KiCad versions.

There is also not much incentive for such a converter, as everybody can easily update to then newer KiCad version once it is stable.

V5.99… project incompatibility may rear its ugly head even from one version of the nightlies to another. This is no remote possibility, it happens all the time. There are very few show-stoppers, though, as most severe bugs are fixed within a few days, if not within one day. But then it depends on your definition of “reliable” as well as “show-stopper”.

It doesn’t happen all the time. File formats are mostly stable at the moment.