Hello,
I’m new to KiCad, so please excuse my questions if they seem very noobish - but the shy doesn’t learn.
I’m currently working through the book “KiCad Like a Pro,” and I’m stuck on one of the projects. I’ve created this schematic:
with net label instead of using wires for VCC(named volt) and GND.
thereafter i created net classes using the schematic setup:
then i moved to the PCB editor and did the following:
i created two copper fill zones one on the f.cu layer for the VCC and another b.cu for the GND
it seems that both the ground and Vcc are connected here :
but the DRC says that those connections are missing:
i’m not sure how to go from here
here is the project if someone wants to have a look :
Kicad forum wont let me upload because i’m a new user - here is google drive link :
google drive link of the project
and also Virustotal scan :
virustotal scan
First, turn off hatching for the zones. It is very rarely beneficial, while it slows down KiCad noticeably (on bigger PCB’s), but more important, It makes your PCB much harder to look at and work with. If you really want hatching, then still turn it off during normal design, and only turn it on again at the end when the PCB is nearly finished.
In your case your first unconnected item is because the track from the net MODE_SELECT goes all the way through over the PCB, and combined with the other tracks it cuts your copper zones into little pieces, that are not connected at all at several places. Combined with the big slot created by the TIMER_RESET track, the “volt” zone around S1 and S2 is not connected at all to the rest of the volt net You can easily see the different islands of your “volt” net if you turn off the hatching and then highlight the volt zone by selecting it.
In general some rules for a good design on a 2 layer PCB are:
- Dedicate one layer to a GND zone (usually the bottom layer).
- Draw all tracks on the other (top) layer.
- Try to avoid hop overs / unders. Most often it’s better to draw longer tracks on the top layer, then to use via’s and draw parts of tracks on the bottom (copper plane) layer. If you really have to use via’s, make the hopunders as small as plausible, just like you have already done with most of them.
- Use decoupling capacitors for all footprints. (the generic 100uF ceramic capacitor is all right for most (beginners) designs. When you get tho high speed stuff (DDR4, FPGA’s, etc) this is not adequate anymore and better and more complex strategies are needed. For beginners, even put decoupling capacitors close to connectors. (They help with mitigating the effect of noise coming into the PCB from external sources, and also filter out noise leaving the PCB (wires act as antenna’s).
- For power, you don’t have to draw a zone. Using some (usually thicker) tracks is plenty when combined with decoupling capacitors and a decent GND zone.
Things like this are also common constructs made by beginners:
This section has 3 hop unders. If you put the 3 vertical tracks closer together, they can be replaced with a single hop under on the diagonal track. But this is a very local solution just to indicate the methodology. It’s a way of thinking you have to learn and avoid such things. (It is one of the things humans can relatively learn easy to do better then auto routers).
Another remark: You drew the zone outlines close to Edge.Cuts, and this is bad practice. It can hide problems with Edge.Cuts, and cause other problems, such as on the left side of S1, where the zone (almost) would have run around the switch on the left side. I usually draw my zones as very big pentagons around the PCB. This has a few advantages:
- It makes the zone very easy and quick to draw.
- It makes the zone easy to select unambiguously (In older KiCad versions, zones could only be selected by their edges, and this is a method I actually preferred. There is just too many selectable things on a PCB).
- It makes any problems with Edge.Cuts very obvious on Gerber files. If the zone boundaries lines on Edge.Cuts closely, then problems may go unnoticed until you have a finished PCB that does not work.
In your schematic, you also have a mix up with local labels and power symbols. Both R1 and R2 are connected to a GND power symbol, while all other locations of GND use local labels. This is allowed by KiCad and it works, but it is not very clear to humans reading your schematic.
“Ratnest” lines can be a great friend. These lines visually show you which parts still need connecting to match your schematic. Unfortunately, these lines only show the closest path between two objects, and not the most convenient path for you to connect objects.
Often, when troubleshooting problems at this stage of a busy PCB, they can often be missed.
I’ve found, when checking ratnest lines on a near completed PCB, it can be very helpful to temporarily both increase the width and change the color of ratnest lines to make them more visible.
Ratnest line thickness can be increased in Preferences > Preferences > PCB Editor > Editing Options.
Ratnest Line color can be changed by clicking on the color tab in the Appearance Manager.
Note: The Objects tab needs to first be selected. I have changed my color to green.
NOTE ALSO:
To change color you must first change your Color Theme from “Kicad read only” to a personal theme.
To do this use Preferences > Preferences > PCB Editor > Colors. (Color themes can also be changed in Schema., Symbol & Footprint Editors)
Up the top you will see “Theme” with “Kicad … (read-only)” followed by an arrow, in the selection box.
Click on the arrow. Click on “New theme”. Type a name in the newly opened box, then OK.
You will now have a new theme with exactly the same colors as the “Kicad read only” theme, but you will be able to change color or alter the saturation or intensity of any colors you wish.
There are also a number of other “Color Themes” available from the “Plugin & Content Manager”.
I hope these comments help you to “Learn like a Pro” 
There are likely multiple zone islands on the front layer. You see that one of them is connected, but some might be missing. Kicad is drawing the light blue ratsnest lines between unconnected items or zone islands.
wow guys thank you so much for the detailed answer, what a great community!
i will be working on it tomorrow and delve into your answers
thanks!
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thank you so much the detailed answer - a couple of points i am not sure i completely understand:
what does it mean to use decoupling capacitors for all footprints? should i put a capacitor in line with every Vcc connection i make - so lets say for u1 pins 29 and 23? how do i decide to which pin i also attach a capacitor?
in your follow up replay you mentioned that it is not good to user power symbol and also local label. should i just use local labels for GND and Vcc and kicad will understand that its driven?
after reading kicad documentation im not sure when i should use net classes from the schematic editor menu on the right and when i should use the net-class assignments from the schematic setup?
also, in my second second replay ( with the image of the schematic setup) i don’t understand why GND net-class assignment works without the / but volt or Vcc only works with the /?
if you could shed some light for me i would really appreciate it!
this is indeed a great tip! i implemented your suggestion and it make everything way clearer now. thank you 
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Don’t forget this qualification:
Change your ratlines back to something more sedate when the board is finished, otherwise when starting a new board you will be totally overwhelmed with ratlines. You probably won’t even be able to find the footprints for the ratlines. 
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- Decoupling capacitors are placed between a power line and GND. There is written a lot of info on their use. Just do a generic search and read a bit.
- Power symbols & Labels. KiCad treats power symbols as global labels. Using power symbols, generally makes the schematic easier to read, because it draws some attention to which lines are for power and GND.
- Net classes. Every net is always in a net class. By default, all nets are in the “default” netclass. Assigning net classes in the schematic setup is most useful if wildcards can be used. For single wires, or wires without labels, you can use netclass wire directives. But it’s also perfectly normal to leave most nets alone and just leave them in the “default” netclass.
- Net names. I believe KiCad internally prepends slashes for netnames that are defined by local labels. If they are defined in a sub sheet, then the name of the subsheet is also prepended. So the label names look like a path name. Global labels are visible in the whole project, so don’t need a path name. Global and local labels with the same name and on the same sheet are also connected.
Thanks for all the help
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