DRC ignore when inside footprint courtyard?


I’m having trouble getting a PCB to pass DRC checks the way I would like. I do a lot of RF design which sometimes requires thin traces with wide clearances. I like to put these restrictions into the net class or fill zone. What always ends up happening though, is that I get DRC violations like the one below:

Is there any way to configure the software to be smart enough not to flag a drc when enterring a component? For example, inside a component courtyard?


You can set the clearance of footprints or even pads separately to the netclass clearance.

Here i set the local clearance of R2 to 0.2mm while having the netclass clearance as 1mm:

This does however not help if the full pad is within the exclusion zone of a trace in the next pad.

Another option (possibly easier) is to change the clearance settings depending on which operation you are currently doing. For example have it quite high while laying down traces, but then reduce it for the production DRC test. (combined with the use of highlight colision + allow drc violations to be able to connect traces to pads)

Hello @Rene_Poschl,

Thank you for your reply. Unfortunately, I am too dumb to understand it :slight_smile: I’ve gone into the local clearance of the following footprint and set it to 0.04mm, however, I still get DRC violation on every pad. Is there a global setting that would apply to all footprints? I would rather not have to do this for every fine pitch part I place.

Any ideas on what I am doing wrong?

Thanks for your help!

Ah found my problem, writing here to document. My net class clearance was wider than the pitch. After reducing that to the process capabilities all is well.

thanks again!

Although I would still be interested in knowing where the global setting for pad clearance is if someone could help me out.


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