DRC errors in first pcb layout

Hi,

I just modified a small PCB layout and did DRC at this site ( http://www.4pcb.com/free-pcb-file-check/). The report says there are more than 1476 violations ! I only have 15-16 components in total (single layer PCB). Can anybody advise. The report is here. BTW KICAD DRC is OK.

Thanks,
Arvind Gupta.

The drill file has not been parsed correctly, so I guess nearly all those errors are spurious.

OK… pls. enlighten me more on what is meant by “drill file has be not parsed correctly”. Do you mean that the software at 4pcb site has not processed the drill file properly?

Thanks,
Arvind Gupta

Yes, exactly. It looks like the positions might be correct, but the drill diameter is way too large, causing all the overlap errors. I didn’t see anything on the 4pcb site that suggests what drill file format they required. You try fiddling with the options in KiCad plot drill dialog, but it would be trial and error I think. Maybe you could call or email them, might get a quick answer?

ETA: Ah, here we are http://www.4pcb.com/gerber-file-guidelines.html

Excellon drill files are used to determine what size holes to drill and where. Plated and non-plated holes need to be included in one drill file, with plated and non-plated holes having different tool numbers.

Requirements: Excellon Format, ASCII Odd/ None, 2.4 Trailing Zero Suppression, English Units, No Step and Repeats.

Not sure what ASCII odd/none refers to, but otherwise it needs to be 2.4 format, inches, suppress trailing zeros. I suggest trying this:

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Yes!! It worked. I selected the above mentioned options and resubmitted the files for DRC. It came out OK. The report is here. Problem resolved

Thanks a lot,
Arvind Gupta