Errors : ErrType(19): Pad near pad
@ (5.3500 in,5.2750 in): Pad 1 on F.Cu, B.Cu, Internal, Non-copper of JM1
@ (5.3500 in,5.3750 in): Pad 2 on F.Cu, B.Cu, Internal, Non-copper of JM1
also getting : ErrType(4): Track near pad
@ (5.5550 in,5.4750 in): Track 0.0600 in, net [/B+MREG] (1) on layer B.Cu, length: 0.2050 in
@ (5.3500 in,5.3750 in): Pad 2 on F.Cu, B.Cu, Internal, Non-copper of JM1
Not using top side metal basically a single sided PCB.
All my footprints use Pads “with all metal layers” selected.
You might need to post the board file.
It’s easy to see that the through hole pads have large clearances which overlap other net’s tracks.
Use push’n’shove routing mode to avoid those automatically, or Highlight Collisions mode to see where the collisions are.
EDIT: or change clearances.
BTW, you didn’t tell KiCad version. You should use 5.1, the latest 5.1.4 is recommended.
This explains a few of the reports but not all of them.
Example the error reported on pad 2 of D15 is not explained by this.
Oh, that’s true.
It looks like the clearances have been set in pads. It also looks like the layout has been designed without help from the push’n’shove router.
One common reason for hard to find DRC errors in THT pads is a short leftover track segment hidden by the pad. Try hiding the footprints and show tracks in outline mode. You can try Edit->Cleanup tracks.
You can also click on each red arrow and see in the bottom of the window which items take part in the problem. Even more handy may be the DRC dialog->right click on a violation description->hover over one of the items. It highlights the item on the board, but unfortunately only if you use a non-windows system or 5.99 nightly builds on Windows.
If you don’t find the reasons of the problems, you have to give the board file here. (I often recommend that anyways if fixing the problem is the most important thing. Otherwise we can go through the details with tens of posts which may be either a good learning experience or wasted time.)
Ok Lets clean up tracks first. Thanks.
I think this maybe as good as it gets. Cleaned up my footprints adding in Courtyard outlines. Worked well on the Wire pads. Remaining Pad issues have nothing to do with the bottom copper not being connected. This is a single sided PCB that can be cut up to fit in a tight spot. Wire jumpers connect between the PCB’s also added a terminal board for single component thermistor if ever needed.
May I ask what files do I need to drop ?
a---- 10/20/2019 6:10 PM 424682 BC348_power_supply_DRC_issues_20191020.jpg
-a---- 10/20/2019 6:00 PM 11376 BC348_power_supply_drc_kicad.rpt
-a---- 10/20/2019 9:27 AM 0 BC348_power_supply_kicad
-a---- 10/19/2019 8:48 PM 10536 BC348_power_supply_kicad-cache.lib
-a---- 10/19/2019 8:45 PM 40144 BC348_power_supply_kicad.bak
-a---- 10/20/2019 7:37 PM 2592 BC348_power_supply_kicad.cir
-a---- 10/12/2019 6:53 PM 13456 BC348_power_supply_kicad.cmp
-a---- 10/5/2019 6:04 PM 113 BC348_power_supply_kicad.erc
-a---- 10/20/2019 7:36 PM 185394 BC348_power_supply_kicad.kicad_pcb
-a---- 10/20/2019 6:20 PM 185389 BC348_power_supply_kicad.kicad_pcb-bak
-a---- 10/19/2019 9:02 PM 455 BC348_power_supply_kicad.log
-a---- 10/20/2019 7:37 PM 42371 BC348_power_supply_kicad.net
-a---- 7/20/2019 3:48 PM 913 BC348_power_supply_kicad.pro
-a---- 10/19/2019 8:48 PM 40166 BC348_power_supply_kicad.sch
-a---- 10/20/2019 9:27 AM 47397 BC348_power_supply_kicad.xml
-a---- 10/19/2019 5:43 PM 527749 BC348_power_supply_kicad_drc_issues.jpeg
At least (for viewing):
- all .sch files
- the -cache.lib file (consider it as part of the sch files)
- the rescue lib (if it exists, if it does then also the symbol lib table)
- the .kicad_pcb file
- the .pro file
If you ever need to share your project for modification then you also need to share any personal libs and if you use local libs then the local lib tables as well.
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