Hi, I have a DRC error for the annular width, please someone help with that.
What IC is that? Why are there holes on the edge of the pads?
Is this meant to mousebites?
Also what is your KiCad version. DRC is evolving fast
Those are castellated Holes.
No those are Castellated Holed, kicad version 8.0
Are the pads actually defined as castellated?
yeah it defined a castellated in fabrication properties
V8.0.what? Early V8 had many minor bugs
what can I do now? can you please help me
One thing you can do is post your full version information, from Help / About KiCad / Copy Version Info and post it here. Or better / also make sure you are using V8.0.6 That third digit is important.
Another thing you can do is make a small test project, zip it up and post it here. It should have a simple schematic, a symbol with this footprint attached (and maybe some extra resistors or such) and a PCB with this footprint, also attached to something.
I am not very familiar with castellated pads myself, and setting up a test project from scratch is some substantial amount of work (maybe half an hour). You can make a copy of your project into a test project in a few minutes. At the moment I am not sure whether you are doing something wrong or whether it’s a bug in KiCad. With such a test project, it’s a lot easier for others to have a deeper look at what is going on inside your project.
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Have you read Castellated edge; plated half holes in board edge ?
I have tried to do it like you, without copper going over the edge, but it’s futile. It doesn’t give any benefit over just using whole annular rings.
VERSION INFO:
Application: KiCad x64 on x64
Version: 8.0.5, release build
Libraries:
wxWidgets 3.2.5
FreeType 2.13.2
HarfBuzz 9.0.0
FontConfig 2.14.2
libcurl/8.8.0-DEV Schannel zlib/1.3.1
Platform: Windows 11 (build 22631), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
Date: Sep 7 2024 02:39:48
wxWidgets: 3.2.5 (wchar_t,wx containers)
Boost: 1.85.0
OCC: 7.8.1
Curl: 8.8.0-DEV
ngspice: 42
Compiler: Visual C++ 1939 without C++ ABI
Build settings:
i can’t upload the test file for you
Try now. Leveled up.
It’s taken me a while to look into this, but I figured I owed you that after asking for a test file myself.
Running DRC on your projects gives:
- Warning: Silkscreen clipped by board edge. Putting your silkscreen lines right on top of Edge.Cuts is indeed a bit of a production problem, and you should fix that.
- Warning: Padstack is questionable (PTH pad hole not fully inside copper) And this is for pads which are marked as being castellated:
I loaded your footprnit in the footprint editor, removed the overlapping silkscreen (This is just a test project), and I removed the offsets of the pads from the hole.
After that, there are still some other DRC violations, but they are unrelated:
** Drc report for test.kicad_pcb **
** Created on 2024-10-31T15:33:04+0100 **
** Found 7 DRC violations **
[lib_footprint_mismatch]: Footprint 'C_0402_1005Metric' does not match copy in library 'Capacitor_SMD'.
Local override; warning
@(145,4500 mm, 74,3600 mm): Footprint C1
[lib_footprint_issues]: The current configuration does not include the library 'DA14531MOD-00F01002'.
Local override; warning
@(146,4900 mm, 80,0000 mm): Footprint IC2
[lib_footprint_issues]: The current configuration does not include the library 'R5F10Y16ASP#X0'.
Local override; warning
@(146,3200 mm, 78,9900 mm): Footprint IC1
[text_thickness]: Text thickness out of range (TrueType font characters with insufficient stroke weight)
Rule: board setup constraints silk text thickness; warning
@(147,2700 mm, 74,4200 mm): Reference 'C1'
[text_height]: Text height out of range (board setup constraints silk text height min height 0,8128 mm; actual 0,7620 mm)
Rule: board setup constraints silk text height; warning
@(147,2700 mm, 74,4200 mm): Reference 'C1'
[text_thickness]: Text thickness out of range (TrueType font characters with insufficient stroke weight)
Rule: board setup constraints silk text thickness; warning
@(149,5600 mm, 75,6300 mm): Reference 'IC1'
[text_height]: Text height out of range (board setup constraints silk text height min height 0,8128 mm; actual 0,7620 mm)
Rule: board setup constraints silk text height; warning
@(149,5600 mm, 75,6300 mm): Reference 'IC1'
** Found 0 unconnected pads **
** Found 0 Footprint errors **
** End of Report **
KiCad does not complain anymore about the Padstack is questionable
Drawing the pads partially outside of the PCB is normal practice for castellated pads. My modified version now looks like:
I also noted you put lines on Edge.Cuts inside the footprint itself. This is probably not the best way to do this. I have designed a few breakout boards myself (although with THT holes, not castellated), and the method I use is:
- Create a project for the breakout board itself.
- Create a footprint with the pad layout, and all the pads.
- Create a symbol for the module. Put it in the schematic, draw the schematic.
- Put the whole shebang in the PCB editor. Draw Edge.Cuts just like any normal PCB.
- Export a step from the finished PCB, attach it to the footprint. (With a Z-offset, I have not thought too much about that part yet).
With this method, I can use the same (THT) footprint both for the module itself, and for projects in which the module is used. This works for THT modules, but not completely for castellated modules. For castellated modules, you want to use SMT pad for the project that the module is used in, and you will probably have to make two separate footprints for the module. One thing you very likely don’t want is to have a big hole inside your PCB in the place where the module should go. But you’ll probably get plenty of warnings about that during PCB design of the PCB that uses this module.
Going back to your original problem: DRC complaining about annular width. I do not get that DRC violation at all, even though I checked and it is enabled in PCB Editor / File / Board Setup / Design Rules / Violation Severity
After that I deleted the (modified) test project, extracted a fresh copy from your zip file and ran DRC again. But with the same results. No complaints about annular width.
I am using KiCad V8.0.6. Maybe that is the difference.
Application: KiCad PCB Editor x86_64 on x86_64
Version: 8.0.6-8.0.6-0~ubuntu20.04.1, release build
Libraries:
wxWidgets 3.2.2
FreeType 2.10.1
HarfBuzz 2.6.4
FontConfig 2.13.1
libcurl/7.68.0 OpenSSL/1.1.1f zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.2.0) libssh/0.9.3/openssl/zlib nghttp2/1.40.0 librtmp/2.3
Platform: Linux Mint 20.3, 64 bit, Little endian, wxGTK, X11, xfce, x11
OpenGL: AMD, AMD RENOIR (DRM 3.42.0, 5.15.0-124-generic, LLVM 12.0.0), 4.6 (Compatibility Profile) Mesa 21.2.6
Build Info:
Date: Oct 14 2024 23:12:55
wxWidgets: 3.2.1 (wchar_t,wx containers) GTK+ 3.24
Boost: 1.71.0
OCC: 7.6.3
Curl: 7.68.0
ngspice: 43
Compiler: GCC 9.4.0 with C++ ABI 1013
Build settings:
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