DRC Edge.Cuts Problem KiCad9

Hello together,

I have problem with custom design rules since I use KiCad9.
I want to create a design rule that ensures that every track has at least 1.8 mm distance to PCB edge (layer “Edge.Cuts”).

Therefore I made 2 attempts for the syntax of the design rule:

Attempt 1:
(rule “M_AC_N Clearance to contour on Layer 8”
(layer “B.Cu”)
(condition “A.Layer == ‘Edge.Cuts’ && A.Line_Width == 0.4mm && B.NetClass == ‘M_AC_N’”)
(constraint edge_clearance (min 1.8mm))
)

Attempt 2:
(rule “M_AC_N Clearance to contour on Layer 8”
(layer “B.Cu”)
(condition “A.Layer == ‘Edge.Cuts’ && A.Line_Width == 0.4mm && B.hasNetClass(‘M_AC_N’”)
(constraint edge_clearance (min 1.8mm))
)

But with both attempts I get the same result. KiCad apparently ignores the design rule and simply checks if 0.5 mm distance is ensured which is specified in the constraints in board setup (see screenshots in attachment).

Can anyone tell me what is false with my design rules?
Or is it even a problem of KiCad9 that it can’t work with these rules?

Kind regards
Andreas


Maybe you’re overthinking this. In PCBNEW, go to Board Setup/Constraints and there’s a setting for ‘Copper to Edge Clearance’.

I know this copper to edge clearance (this value is adjusted on 0.5 mm → See my screenshot).
But in my case I need different distances on each layer due to high voltage isolation. And only way (as far I know) to realize this is the way with own created design rules.

If PCB has simple shape (like rectangle) my first idea would be to use Rule areas. They can work at specified layer list so you can have different rules for different layers.
In past I proposed to add layer specification for margin layer (or something like that). If it would be done you will be able to just draw smaller PCB shape inside its normal shape getting the effect you need (different for different layers).

simple / practical: Is your area really so limited that you can’t afford to use the copper to edge clearance of 1.8mm everywhere?

For the custom rule:
I’m not very good with these rules, but your attempt does not look good. First, your constraint of “edge_clearance” already implies a relation to lines on Edge.Cuts, so you probably don’t have to ad that to the condition. It also appears you want to use “B.Layer == In8.Cu” instead.

What’s the idea of this “A.Line_Width”. Are you using different line widths on Edge.Cuts in an attempt to have different clearances in different parts of Edge.Cuts?

I don’t know the details of your design, but I’m guessing that working with Rule Area / keepout is a better option.

image

Maybe you can do something with the margin layer. I never fully understood that layer, and there is very little info for it in the manual too. It’s tooltip has more info.

image

Reason for my topic ist not space on PCB. I simply need different distances from copper to PCB edge due to HV isolation reasons to housing which is in direct neighbourhood of PCB.

Idea of " A.Line_Width == 0.4mm" is that we draw only PCB edge on layer “Edge.Cuts” with line thickness 0.4 mm to apply these rules only at PCB edge. Inside PCB for normal cutouts we draw these cutouts with different line thickness on layer “Edge.Cuts” to use their standard distance to copper of 0.5 mm which is defined in constraints in board configuration.

Unluckily our PCB has a quite specific shape which is far away from any rectangle due to mechanic integration reasons inside a housing.

Using complicated filled zones is not too complicated so may be using complicated shapes of Rule area is also acceptable :slight_smile:
Example of one my GND zone:
Polygon

Can you explain a little bit how you define and create this Rule areas? This topic seems to be quite special (I can find rarely information on google).

What I shown is not rule area but Filled Zone (I believe Rule area you can define the same way).
When I start to edit it I got handles allowing to shift corners or borders. Right mouse click at handle and you will find how to create/delete corner:

I have never tried to find any information about KiCad at google. It should be in KiCad PCB manual.

You can find a rule in Castellated edge; plated half holes in board edge - #2 by eelik which can be modified for your purpose, to be used with a named rule area instead of a courtyard.

I have no real experience with the design rules, but out of curiosity I implemented this:

(version 1)
(rule “track_edge_cuts”
(layer “B.Cu”)
(condition “A.Type == ‘Track’”)
(constraint edge_clearance (min 2.2mm))
)

The rule is not respected during routing, but afterwards the DRC will find the edge.cuts violation.