Hello everybody!
I am trying to figure out why the custom rule I wrote, is not working when running DRC from PCB_Editor.
Running from kicad-cli it does not work either.
I have a board with two connectors (TPH): ETH1 on TOP and Euro/VME Connector on BOT. The Euro Connector does not have any Net or signal connected hence, it is only for secure the board to its backplane (it’s only mechanical).
The Ethernet RJ45 MagJack is connected. But due to space constraints some pins need to be removed from the Euro/VME Connector, so those pins are simply holes in the footprint with no connections at all.
Running the DRC it gives me this warning:
** Found 1 DRC violations **
[solder_mask_bridge]: Rear solder mask aperture bridges items with different nets
Rule: board setup solder mask min width; warning
@(150.6321 mm, 78.4726 mm): NPTH pad of X1
@(151.0861 mm, 79.7406 mm): PTH pad 12 [Net-(ETH1-Pad12)] of ETH1
I would like to exclude this warnig from the DRC check, so I can finish my project.
Are you very sure you really want to do this? PTH and NPTH are made in different steps in the production process, and thus there are always alignment tolerances. Your holes look like they are quite close together, and as a result this may lead to production problems (I.e one hole overlapping the other due to alignment issues).
One way to reduce alignment tolerances is to define both of these holes as PTH pads. If you give them the same pad number, then KiCad also does not complain about overlapping pads, they are just merged into a bigger pad.
You can always exclude specific DRC violations right in the DRC window itself. Just right click on any violation and then exclude it. A quite new feature of KiCad is that each exclusion can be accompanied with a text comment of why the violation is excluded. This is mainly intended for the next developer (5 years after you left the company) and who then has to do maintenance on the project. But I’m not sure whether this feature was added to KiCad V9, or is only in the nightly at the moment.
Thank your @paulvdh for the quick answer, but I know the process well enough, thanks.
As soon as the bottom component is a simple placeholder without any pin nor connection in the hole (it’s simpy a drill hole), I would like to rid of the warning with a custom rule.
After all I know in production line the bottom component (X1 connector) is the only with hand soldering, hence some of the pins are removed and some plastic will be ripped off…
Any clue for the rule to get the warning goes away?
And last but not least, I cannot set this warning as exclude in the DRC window. Well, I excluded it, but at the next run of the DRC check it will complain again… May be a bug in KiCad V8?? Other warning can be excluded easily…
…and please don’t tell me to switch to KiCad 9… Maybe in the next project.
To me the appearance of the warning in the first place is a bug. There are no two nets which could be bridged. Not being able to exclude it (if nothing else is done between the DRC calls) is also bug, but it may be related to the first one.
You probably could find a custom rule to do it, but if a rule you are trying doesn’t seem to work, how would you know it’s not the second bug above?
If you want to be part of development of KiCad you can test with the nightly builds and report bugs if they are still there and haven’t been reported already. Otherwise, just ignore the problem.
Thanks @eelik for your answer.
I suppose the only way to get rid of this error is to set to a very small soldermask margin override for the NPTH hole/drill and reduce the same soldermask margin override for the PTH pin.
I will check.
Otherwise I am unable to find the custom rule to rule it out…
Sometimes I misjudge the experience level from a user by just reading a post…
I think not. I had some trouble in interpreting what is going on exactly, and to me it seems the DRC violation is correct. There is an extra solder mask aperture expansion here, and the solder mask expansion of the NPTH overlaps with the copper of pad 12. But then the question becomes: Why is solder mask expansion applied to a NPTH? Is this a bug, or intended behavior from KiCad? Solder mask expansion is not the most used feature, which makes it more likely there are some bugs in this area.
@gianlucarenzi What is the rule you attempt to use? I’m guessing, but maybe you swapped “A” and “B” in the rule and are checking the wrong clearance.
There are different ways to set solder mask expansion (and clearance) overrides. You can set them on a footprint basis, but also for single pads, and when an “override” is set to zero, it’s inherited from another level. I just noticed the checkbox below in the Footprint properties. Looks like this is very close to what you want.
Good for you it works. I am guessing it would also work if you set the Solder mask expansion for either the pad or the whole footprint to a very small (maybe even negative) value.
But there are no two nets to bridge. Maybe the DRC check uses the copper (with a net) and the non-plated hole (with no net)? I don’t think that’s the purpose of that specific check.
I think this is the normal procedure. There’s the mask registration error and drilling tolerances. To be honest I don’t see this as very important, but it’s “nice” that the drill and the mask don’t touch. Also, if the drilling is done first, the mask may flow into the hole if there’s no clearance.
I am guessing that DRC check the clearance between the solder mask (regardless of whether it belongs to a net) and “Items from another net”.
I also thought some more about that. (And experimented a bit). I guess it’s nice if you can create a solder mask aperture for a NPTH. This prevents pinching of the solder mask when used as a mounting hole, when lock washers are used, small pieces of the solder mask may crumble if pinched. It would be silly if you would have to place an aperture pad over an NPTH just because you want to remove solder mask (regardless of why you would want to do that) Solder mask clearance is standard part of a pad (and NPTH) so it’s logical to just use it.
But I do think I found a bug:
When you edit a NPTH in the Footprint Editor, you can turn off the solder mask layers:
And when the solder mask layers are turned off, solder mask expansion is still applied in the footprint on the PCB. (At least, that is how my KiCad V8.0.9 behaves).
Maybe in the next project. 
