DRC : Clearance violation (net-class default, clearance 0.2000mm, actual 0.1500mm)


When trying to create the GND plane, I got these errors “Clearance violation (net-class default, clearance 0.2000mm, actual 0.1500mm)”, what these errors are for ? see the images below :

What clearance have you set in the Zone properties ?


Your board setup defines the clearance for the Default Netclass.

Here is the board setup, does this mean that the Routing shouldn’t be less than 0.2mm?

what these errors are for?

These errors show you that the clearance between copper items (tracks/pads) of different nets have not enough clearance (The clearance is needed for isolation).

In your case these errors are independent from the GND-zone: the error description shows the involved items, in your case all errors are between tracks and other tracks/pads.

Not sure how you got into this situation, but there are two options to repair the board:

  • change layout to increase the clearance between your tracks and the pads
  • decrease the needed clearance value for the DRC check. Be careful, this reduces the isolation capability and maybe conflicts with the manufacturer production possibilities.

The clearance values for the DRC are set in these dialogs:

  • board setup → design rules → constraints
  • board setup → design rules → netclasses

The error message shows you which value is violated (in your case the netclass default value)

what should I do in that case, do I have to reduce the track width to avoid this error?

You may reduce the track width, but for the trackwidth there is also a minimum (also defined in the dialogs shown above) width defined. So you not go below this minimum value.

It’s better to move (use the “drag” command) the tracks away from the pads + the other tracks. There is plenty of space on the board, there is no need to place the tracks with minimum distance.
Depending on the used router mode (main menu bar → route–>interactive router settings) drc collisions are highlighted with green color during dragging of a track.
Try to solve one drc collision after the other, run a DRC check after each madification to see if the number of clearance errors is reduced. Start with a task, for instance the tracks on the 2-pin footprint (pinheader?) on the right side.

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Thanks for the guidance, so clear! I tried to work on replacing the components to avoid that the tracks touch the pads but there’s some type of component that has the flag while there’s no track that is touching their outline! Also, appearently I’ve another type of error as shown below :

clearance error:
if you look at the error description for the clearance error I guess you will see something like “clearance between Pad1 - Pad2”. This means that the two pads are to close together and violating the minimum clearance requirement.
If you look at your second picture you will observe the small blue outline around each pad. This is the needed clearance around each pad/track, no copper from a different net/potential must be in this area. And on your second picture you see the pads are inside the clearance area of the opposite pad. Conclusion: the choosen footprint is to small for the choosen clearance value.
advice: Choose a bigger footprint - a bigger footprint provides more space (== clearance) between the pads.
How do you choosen the current footprint in the first place?
advice: always try to use bigger footprints - only if the space is really restricted (if you want to design the next generation smartwatch) go to smaller footprints.

regarding your second question:
“silkscreen clipped by soldermask”: at some places your silkscreen drawings are placed on top of pads. On these places you will later solder the components, so silkscreen color on these pads is not nice. Either move the silkscreen (probably reference designators) away from the pads. Or rely on the pcb manufacturer, most remove the silkscreen from the pads automatically. Notice that this can influence the readability of the silkscreen writings.
“silkscreen overlapping”: two different drawings on the silkscreen layer are on the same place and overlapping each other. This could influence the readability. Move the silkscreen writings/drawings if this is important to you.

notice: the drc with it’s many many checks (see board setup–>design rules–>violation severity for all available drc checks) includes important and not so important checks. Clearance violations are very important and normally must be avoided. Silkscreen violations depends on your aesthetic requirements.

/ silkscreen overl


Problem Solved! Thank you!

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