DRC Check for trace width spacing?

[sg.giffin]

As the title states.

[PCB_Wiz]

The question/issue is not clear.

DRC works on a copper-clearance basis, since that is what bothers PCB FABs.
DRC/FABs do not care about the centre line pitch of the traces, just the size of the gap.

Of course, if you know the trace width, and know the clearance, those do combine to give a trace centre line spacing.
eg you might choose 8 mil traces and 7 mil gaps, to give a 15 mil natural minimum trace centre line pitch outcome.

[Sprig]

Did you mean, “Does the DRC check for trace width and spacing?”

This is kind of an odd question; actually two questions.

1. There is no need for the DRC to check trace widths. The Design Rules Editor will not allow generation of traces that are smaller than the minimum track width.

2. As above, provided that DRC violations have not been allowed, there should not be a need for the DRC to check trace clearances. However, there is a setting in the DRC, "Report all errors for tracks (slower) and this may (or may not) check for proper clearance spacing.

[Rene_Poschl]

Never trust the run time DRC that does not allow you to do things. Always run a full DRC that really checks everything before ordering your board.
This check does use the minimum width settings and minimum spacing of both the assigned net class and the global settings to arrive at a report.

A thing to keep in mind is that the check is net based. So if you have two traces of the same net too close together kicad will not flag it. (So if you have a case where you would like this to be checked you need to use net ties to give these two traces a different net)