Drawing a wire between 2 pins

Hello!

I have the following problem. Two problems in fact.

1. I’m using a 1.27mm pitch connector. Its holes are 0.6mm in diameter, and the outer diameter of the hole metallized part is about 0.9mm. Therefore 0.37 mm are remaining between these patterns. As the manufacturer can accept 0.125 traces with 0.125 clearante, it’s a bit too wide for the top and bottom levels. However, the inner levels have a diameter of 0.8, which makes it possible to draw a 0.125 mm wire in the middle of 2. Apparently Kicad doesn’t allow me to draw this. I have tried to draw it in the inner level, but apparently for Kicad, it’s too thick to go between 2 pins. Does it mean that the inner restrings are similar to the surface restrings? Is it possible to change that to have a smaller inner restring?
If yes, how?

2. How to refresh the copper plane? If I draw a wire, then the copper plane shoud leave space for it. Is there any way to refresh the drawing so that my new wire is taken inco account? As you can see, the wire pulled from reset cuts the power lines without making its own path.

Thanks,

Pascal

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Hello!

Now concerning the method to go between pins, any hint? For example in this case, I would like to pull pin 6 (on the right) between pins on the other side (e.g 1&3 … 7&9). And apparently Kicad refuses this.
Thanks for any hint.

Pascal

You need to check the combination of track width and clearances.

Hello!

Thanks for your reply. That’s what I did. I have checked the design rules and I have set up the clearance to 0.125 and the track width similarily to 0.125. This means that 1.27 - 0.9 (size of the through hole restring) = 0.37 is too small: As the maker will not accept less than 0.125 in this class of price, then I need 0.375. Now if I had 0.8 in the inner layers instead of 0.9, then I would get a space between 2 restrings of 0.47 which allows to draw a track of 0.125.
Now with the software I was using previously (eagle), there was a way to set smaller restrings for the inner layers, therefore my question above:
-> Is it possible to set a different size for restrings in the inner layers (for example 0.8 instead of 0.9) ?

Now I have checked the settings of the copper pouring. Maybe the problem is not related, I don’t know. However, I have the following issue. When I chek the characteristics of copper zones, there is a clearance, a minimum width, etc… I tried to change to the same rules. Clearance to 0.125mm and also minimum width. And I have exported to other zones in order to use the same settings everywhere. Then I pressed OK.

The problem now is that if I select again the copper zone tool, the settings are back to what they were.
-> Is this a bug, a known issue?
-> How do I change these settings,

Thanks,

Pascal

KiCad uses the same “restring” aka pad size on all layers, it is not possible to change that.

What kicad version do you have? I have just tested it with ubuntu 4.0.7 and nightly (2017 09 25) and it works fine. The way you are doing it it’s the right one: click Export and click OK.

It is not possible. But you can set off the DRC for a moment, lay the tracks and set it on again. The DRC will complain in the end, but you will know itis OK for the inner layers.
Or set the radius to 0.8, trace the inner tracks and set the radius again to 0.9. Same DRC complaints, anyway.

Hello!

I’m using the latest stable release, I think it’s 4.0.7, that I have downloaded a few weeks ago before starting. So my environment is fresh installed and should correspond to the latest version of both programs and libraries.

As for setting off the DRC for a moment, that may be fine, but the PCB make is quite strict for the rules and will not admit any exception. Their PCBs are perfect and reliable, but the counterpart is no exceptions to their rules.
Does anyone know if this functionality will be added in the future (different restrings diamaters in inner layers)?

Thanks,

Pascal

Took me a while to to at least think I understand what is being talked about here. Kicad assumes the copper annulus ring is the same on the inner copper layers when in reality it is just the the inner coating of the plated through hole? Therefore it throws DRC errors when routing the inner layer even though the copper doesn’t in fact exist on those inner layers?

Hello!
Here is an explanation with a screen shot which will be easier than with words.
The attached picture is the setting panel in Eagle. What they call restring is what you call annulus ring. It’s possible to configure the inner rings and outer ring widths. In this case, 0.1, and 0.15m respectively. Therefore if I have a 1.27mm pitch connector, the holes being 0.6mm brings me to 0.6 + 2x0.15 = 0.9 on the external layers. As the pitch is 1.27, the space between 2 rings is 0.37. But as both thickness and clearance are 0.127, 1 width + 2 clearances bring me to 0.375. Therefore 0.005mm are missing, and I cannot draw a wire between 2 pins.
But in this configuration, I can draw the wires in the inner layers because there is more space (0.47 instead of 0.37). As I use a lot of these small pitch connectors, I would like to have the same freedom in Kicad.

By the way, I have tried to set the min width and clearance to 0.1, but Kicad still refuses to draw through. I think I have no other choice than making my own footprints. By the way, another question: I wanted to see exactly how much space I have in the inner layers, so I tried to have only one copper layer and nothing else. But there is no way to remove everything but that layer, even when unchecking all the layer and all the renderinhg. I still have the hols with their net names that I can’t get rid of. Is there a way to see only a single copper layer and nothing else (except going into the Gerber process)?

Thanks,

Pascal

As Bob stated, the same annulus exists on all layers. it would be nice to have control over the size of the annulus on inner layers and I think this has been discussed, not sure what the verdict was.

There is no workaround I am aware of.

You woudln’t break their rules. You would still have a 0.375 mm space in the inner layers. You would get a kicad DRC warning/error in a specific place you certainly know there is not such an error (based on your manufacturer’s capabilities).

PD: sorry, I have seen my gerbers: the annular ring in the inner layers is the same as in the outer layers. I thought there would not be a copper ring in the inner layer if this layer were not connected.

The work around is very risky: a gerber with the footprint annular ring of 0.9 for the outer layers and a gerber with the footprint annular ring of 8 for the inner layers.

Hello!

You woudln’t break their rules.
In the case there is not enough space, yes, I would break their rules.
Their rules are 0.125mm minimal track and 0.125mm minimal space. As there is only (1.27 - 0.9) mm (i.e. 0.37mm) for one track width and one minimal distance each side, according to their rules, I need 0.375 and I have 0.37 only. I’m sure the 5µ difference wouldn’t make a big problem and I could take the risk, but as it doesn’t fit their rules, then thhey will either refuse to do it or bill accordingly with 0.1mm DRC instead of 0.125.
Right now I made a new pattern set with 0.88 mm pads instead of 0.9. In this case, I get 1.27 - 0.88 or 0.39 mm, which is wide enough for 1 track and 2 spaces. I have trouble seeing the new pattern, but this will be a separate question in another message.

Thanks,

Pascal