The draft mentions IPC-7351 twice, but not IPC-2581.
I can’t imagine how anyone could define a technical standard which is both reasonably elegant and certainly capable of communicating all the information which might be relevant to procuring components for PCB assembly. So I think they should abandon this goal.
I can imagine the proposed extension to the Gerber format being elegant and sufficient for generating pick and place data, part of which would be identifying each component as one of set of one or more identical components for the purpose of placement and procurement. Then the procurement arrangments can be as the parties desire, with robust standardised references to each such set and individual component in the new Gerber files. As far as I know, this would be a huge step forward, especially since they are planning for this capability to support visual and I guess automated checking of the placement of components with respect to the pads defined by the other Gerber files. I assume that in the final version, this will support courtyards so the assembly company can check that the design doesn’t violate courtyard-related placement constraints, rather than finding out the hard way after the board is assembled.
The draft is aimed at specifying this for a single board or board set. This would involve a direct match with Gerber files for a single board or set of boards. But assembly companies are typically dealing with a panel of such boards or board sets. So I guess the assembly company would be given the conventional Gerber files for the panel, and a separate set of Gerber files, including the new ones regarding component placement, for just a single board or board set. It would be up to the assembly company to process the data into a form suitable for whatever pick-and-place machines they have.
This seems like a good idea to me, rather than expecting the new standard to cope with placement data for an entire panel.
There are quite a few things to consider at this level. Firstly, the board or board set may have fiducials to orient the placement of components within it. I think the new standard should have some specific provision for specifying these, for both sides if necessary. Otherwise, the identification of such items on the PCB as fiducials must remain a manual task, with associated costs and likelihood of error.
Although I am yet to have a board automatically assembled, it seems to me that the assembly company generally has to do a lot of very tricky manual work to generate the procurement and placement data they need from the files which are currently supplied. While traditional Gerber files are a starting point, the “position” file, as far as I know, has no standardised format. If it is anything like what KiCad produces (top side only, millimetres, CSV format):
http://www.firstpr.com.au/temp/kicad/example-top-pos.csv
Then there is non-trivial work to do on this data before it can be used for anything.
The first task is to identify which lines refer to multiple components of the exact same type from the point of view of assembly (and therefore procurement). In this example file, this must be done by finding all the lines with matching Val and Package (footprint name) fields, where Val values are, for instance just “3301” for a 3.3k resistor, with nothing about tolerance, power handling capability etc.
One might conceivably have multiple capacitors on the board with the same Val, such as “224” and the same footprint “CAPC200X125X60L40N-2012i0805” but different voltages and/or tolerances, neither of which appear in the .pos file. I guess it is the responsibility of the designer to sort the lines by Val and then Package and to manually check the results to make sure the groups of components which result truly reflect the design intention, and are not corrupted by typos, different ways of specifying the Val etc.
I guess that the assembly companies have tools to automate this and produce clearly identified sets of components of the exact same type to further stages of their workflow. If so, it would be nice for designers to have similar or the same tools.
The task of checking a .pos file’s validity seems especially difficult, at least for designers - and I guess for assembly companies even with appropriate software. There is a free (beer, not open source) Windows only program which checks placement data against Gerber files:
https://www.compuphase.com/visualplace/visualplace_en.htm
It was most recently updated in March, has a 110 page user manual and is the result of many years of work. I haven’t seriously tried to use it yet, but I should.
I understand it is common practice to have a white (or whatever the top legend screen print colour is) dot somewhere on each board or board set, as a “bad mark”. If that section of the panel fails electrical test at the PCB manufacturing company, then someone or something colours the dot black. Then the pick and place machine can be programmed to inspect the dot and avoid placing any components on that section of the panel if it is coloured in. This is the sort of thing which probably should be specified in the standard as well.
The document I was sent looks to me like early work, nowhere near the state it would need to be to achieve the pick and place functionality. Since I know nothing about Gerber formats and have only limited experience with PCB assembly - my first project will be assembled in the next few weeks - I can’t contribute much to the draft. Since it was sent to me privately, and since it is being revised, I won’t make it public or discuss any details about it.
I imagine that Ucamco will send a current copy to anyone who writes to the email address I mentioned - and that they will appreciate any feedback you can give.