I noticed something that I hadn’t seen before and I can’t figure out what causes this to happen.
As you can see from the video, after hitting 6, I’m dragging the traces to the right and it bumps out to the left before going right. Anyone have an idea what’s going on here and how to cure it?
Apologize if this is a FAQ, I have looked and not been able to find anything on this. Any pointers welcome.
Thanks,
Christian
PS: yes, this is 5.99, version details are in the video description.
This looks like a bug. Make sure you have the latest nightly build, create a file with which this can be reproduced by others and attach it here. If it still looks like a bug, please report it to gitlab.
I’ve seen this same thing quite a while ago and from what I can remember it’s because the settings of the differential pair make it’s center lines further apart then the pad pitch and KiCad has trouble with getting the tracks to the right differential pair gap.
This may have been reported on gitlab and fixed about a year ago, so this may be a regression, but I can’t really recall any details. It’s just too long ago. I also spend a few minutes on Gitlab to try to find it, but had no success.
Can you post which footprint you’re using, and what settings you have for the netclass of the differential pair?
Or better:
Make a copy of your project.
Remove all schematic symbols, footprints and tracks that do not connect to that differential pair.
Check if it’s still reproducible.
Post the remains of the project here.
As a workaround, It may work if you just draw the differential pair, then go back to the start, delete the last few segments, and then connect the cleaned up stub again to the pads.
I’m guessing here, but you may be able to improve the behavior by experimenting with PCB Editor / Route / Interactive Router Settings
Will do. It’s the latest build. I’ve seen a bunch of other weirdness in the dp routing as well… like traces that start from point A but when drawn from B they won’t connect to those started from A even though the +/- fits. Happens to me at vias and traces on same layer. And then the mystery version where you start a dp trace from a point, click/double click, and the new trace disappears*. Were there changes in the dp code somewhat recently? Driving me nuts with eth/hdmi/usb traces on this board
no error message, no highlighting of conflicts, just vanishes.
Pick any of the HDMI pins on the right-hand Hirose DP connector (e.g. 172/173 like in the example above), hit 6 to route the dp for the repro of the clip above. The clearance is less on those than on the, for example, eth pins on the left hand connector where this doesn’t occur.
Looks like the weird “two ends of the same dp pair won’t connect” issue is a collision? I don’t get it. The traces of latch, it doesn’t show anything in push and shove router, but when I switched to highlight it marked one of the vias as green. (Or the traces from the pads if you go the other way from the vias out to the pads). Weird thing is, sometimes this works fine, sometimes it doesn’t. Is it a setup issue? Where do I look? (same project as attached above). Is this expected?
The collision also moves. If you separate the vias, and then start tracing from the
All net names with “HDMI” are set to the default net class, even though you have made a net class for “HDMI / USB DP”.
Just to make the huge difference even more clear, I used Assign Net Class, selected New net class “HDMI/USB DP” and clicked on Assign To All Listed Nets and routed a part one of the HDMI Pairs.
Because the center lines of the DP-pair are now (much) closer to each other then the pitch of the pads they connect to, the bug does not manifest itself.
I also find the track settings for these net classes extremely thin. 0.0762mm shows as 3mils in those other units.
I had a look at eurocircuits and Aisler and they both have a minimum track width of 0.1mm, and as a rule of thump it’s not recommended to set your design rules to the minimum that a PCB manufacturer can make.
In my experience it’s easy to get lost in actual sizes and proportions when designing a PCB. Is this the case, or are your numbers correct?
@paulvdh, the numbers are a result of me playing with the sizes for hours to figure out if I could determine what was causing it. No, I’m not planning on routing anything as small as 3mil. Thanks for paying attention and pointing that out, tho!
That’s OK.
It would have been slightly more convenient if your project did not have any settings that looked “weird”, but I replicated the problem in a project I made myself (and posted on gitlab) just to verify and exclude that it was not made by any settings you made in your project.
Thanks for paying attention and pointing that out, tho!