'Don't cares' for address bus lines

[jaevans]

Greetings,

I’m not sure what to call this, but here goes. I’m laying out an external memory and i/o board for an old processor trainer and for RAM the order of the address pin connections to the address bus don’t really matter. In fact, I’ve seen designs where, say, A0 on the address bus goes to A4 on the RAM chip, all this to make routing traces simpler.

Is there a way to tell KiCad that you don’t care how the address lines are connected as long as all the subset of lines of the address bus do go to the RAM chip ? This could reduce the number of vias between the bus and the chips.

Thanks,
John

[kenyapcomau]

I had a similar requirement for a bus latch chip, the 373. I didn’t care how the 8 latches were associated with the address lines, as long as the input and output matched. I just looked at the PCB layout and iteratively adjusted the assignment of the latches for better routing. I don’t know if there’s a faster way to do it.

clock.pdf (72.4 KB)

[pedro]

Maybe the swap_pins plugin can solve this problem.

MitjaNemec/Kicad_action_plugins

[der.ule]

I believe that WireIt can help you too

WireIt: PCBNEW plugin for adding/cutting/swapping wires in the physical layout

I’ve released WireIt, a PCBNEW plugin that lets you add nets, remove nets, and swap pins on the physical layout. Changes made in the layout can be dumped to a file for backannotation into the schematic. There is a short video demonstrating its use. I’m using WireIt in conjunction with PadPainter to do I/O pin assignments from an FPGA to surrounding peripherals so that the wiring is as crossover-free as I can make it.

[jaevans]

Looks like some possibilities here. I’ll give each a try when I get to this point.

Thanks much,
John